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ds07-13729-1e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90370 / 375 series mb90372/f372/f377/v370 n n n n description the mb90370/375 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed real-time processing. the instruction set is designed to be optimized for controller applications which inheriting the at architecture of f 2 mc-16lx series and allow a wide range of control tasks to be processed efficiently at high speed. a built-in lpc interface, serial irq and ps/2 interface simplifies communication with host cpu and ps/2 devices in computer system. moreover, smbus compliant i 2 c* 2 , comparator for battery control and a/d converter imple- ments the smart battery control. with these features, the mb90370/375 series matches itself as keyboard con- troller with smart battery control. (continued) n n n n pac k ag e 144-pin plastic lqfp (fpt-144p-m12)
mb90370/375 series 2 (continued) while inheriting the at architecture of the f 2 mc* 1 family, the instruction set for the f 2 mc-16lx cpu core of the mb90370/375 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, the mb90370 has an on-chip 32-bit accumulator which enables processing of long-word data. *1 : f 2 mc stands for fujitsu flexible microcontroller and a registered trademark of fujitsu limited. *2 : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. n n n n features ? clock ? embedded pll clock multiplication circuit ? operating clock (pll clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 mhz to 16 mhz) . ? minimum instruction execution time of 62.5 ns (at oscillation of 4 mhz, four times the pll clock, operation at v cc of 3.3 v) ? cpu addressing space of 16m bytes ? internal 24-bit addressing ? instruction set optimized for controller applications ? rich data types (bit, byte, word, long word) ? rich addressing mode (23 types) ? high code efficiency ? enhanced precision calculation realized by the 32-bit accumulator ? instruction set designed for high level language (c) and multi - task operations ? adoption of system stack pointer ? enhanced pointer indirect instructions ? barrel shift instructions ? program patch function (2 address pointer) ? improved execution speed ? 4-byte instruction queue ? powerful interrupt function ? priority level programmable : 8 levels ? 32 factors of stronger interrupt function ? automatic data transmission function independent of cpu operation ? extended intelligent i/o service function (ei 2 os) ? maximum 16 channels ? low - power consumption (standby) mode ? sleep mode (mode in which cpu operating clock is stopped) ? timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped) ? stop mode (mode in which all oscillations are stopped) ? cpu intermittent operation mode ? watch mode ? package ? lqfp-144 (fpt-144p-m12 : 0.4 mm pitch) ? process ?cmos technology
mb90370/375 series 3 n n n n product lineup (continued) part number parameter mb90v370 mb90f372 mb90f377 mb90372 classification flash type rom mask rom rom size 64k bytes ram size 15.7k bytes 6k bytes cpu function number of instruction : 351 minimum execution time : 62.5 ns / 4 mhz (pll 4) addressing mode : 23 data bit length : 1, 8, 16 bits maximum memory space : 16m bytes i/o port i/o port (n-channel) : 16 i/o port (cmos) : 72 i/o port (cmos with pull-up control) : 32 total : 120 16-bit reload timer reload timer : 4 channels reload mode, single-shot mode or event count mode selectable 16-bit ppg timer ppg timer : 3 channels pwm mode or single-shot mode selectable bit decoder bit decoder : 1 channel parity generator parity generator : 1 channel selectable odd/even parity ps/2 interface ps/2 interface : 3 channels 4 selectable sampling clocks lpc interface lpc bus interface : 1 channel universal peripheral interface : 4 channels ga20 output control : for upi channel 0 only data buffer array : 48 bytes lpc standby (able to work in stop/tbt/watch mode) yes no yes no serial irq controller serial irq request : 6 channels lpc clock monitor / control uart with full-duplex double buffer (variable data length) clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used i 2 c i 2 c (smbus compliant) : 1 channel support i 2 c bus of philips and the smbus proposed by intel selectable packet error check timeout detection function pc arbitration under a paticular condition* 2 no no yes no
mb90370/375 series 4 (continued) *1 : varies with conditions such as the operating frequency (see section n electrical characteristics) , assurance for the mb90v370 is given only for operation with a tool at power supply voltage of 3.0 v to 3.6 v, an operating temperature of 0 c to +25 c, and an operating frequency of 1 mhz to 16 mhz. *2 : i 2 c can detect the arbitration lost when another i 2 c starts another communication at the same time. *3 : after reset, pf5 to pf7 serve as general purpose i/o pins in mb90f377; however, these pins serve as v1, v2 and v3 function in other products. part number parameter mb90v370 mb90f372 mb90f377 mb90372 multi-address i 2 c multi-address i 2 c (smbus compliant) : 1 channel support i 2 c bus of philips and the smbus proposed by intel selectable packet error check timeout detection function 6 addresses support alert function bridge circuit three bus connection routes can be switched by i 2 c / multi-address i 2 c comparator a comparator that can change the hysteresis width is contained battery voltage, mounting/dismounting and instantaneous interruption can be de- tected parallel and serial charging/discharging external interrupt 6 independent channels selectable causes : rise/fall edge, fall edge, l level or h level key-on wake-up interrupt 8 independent channels causes : l level 8/10-bit a/d converter 8/10-bit resolution : 12 channels conversion time : less than 6.13 m s (16 mhz internal clock) 8-bit d/a converter 8-bit resolution : 2 channels lcd controller/driver* 3 up to 9 seg 4 com selectable lcd output or cmos i/o port without lcd controller/driver same as mb90f372 low-power consumption stop mode / sleep mode / cpu intermittent operation mode / watch mode process cmos package pga256 lqfp-144 (fpt-144p-m12 : 0.4 mm pitch) operating voltage 3.0 v to 3.6 v @ 16 mhz * 1
mb90370/375 series 5 n n n n package and corresponding products : available x : not available note : for more information about each package, see section n package dimensions. n n n n differences among products memory size in evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. the following items must be taken into consideration. ? the mb90v370 does not have an internal rom, however, operations equivalent to chips with an internal rom can be evaluated by using a dedicated development tool, enabling selection of rom size by settings of the development tool. ? in the mb90v370, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h are mapped to bank ff only. (this setting can be changed by the development tool configuration.) ? in the mb90372/f372, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h are mapped to bank ff only. package mb90v370 mb90f372 mb90f377 mb90372 pga256 x x x fpt-144p-m12 x
mb90370/375 series 6 n n n n pin assignment ? mb90372/f372 (top view) (fpt-144p-m12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 p40/psck0 p41/psda0 p42/psck1 p43/psda1 p44/psck2 p45/psda2 p46/clkrun p47/serirq p50/ga20 p51/lframe p52/lreset p53/lck p54/lad0 p55/lad1 p56/lad2 p57/lad3 rst vcc vss x0a x1a pa0/alr1 pa1/alr2 pa2/alr3 pa3/aco pa4/ofb1 pa5/ofb2 pa6/ofb3 cvcc cvrh1 cvrh2 cvrl cvss pb0/dcin pb1/dcin2 pb2/vol1 p77/ppg1 p76/ui3 p75/uo3 p74/uck3 p73/ui2 p72/uo2 p71/uck2 p70/ui1 p67/uo1 p66/uck1 p65/int5 p64/int4 p63/int3 p62/int2 p61/int1 p60/int0 pd7/ppg3 vss vcc pf7/v3* pf6/v2* pf5/v1* pf4/com3* pf3/com2* pf2/com1* pf1/com0* pf0/seg8* pe7/to4/seg7 pe6/tin4/seg6 pe5/to3/seg5 pe4/tin3/seg4 pe3/to2/seg3 pe2/tin2/seg2 pe1/to1/seg1 pe0/tin1/seg0 p82/alert 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 pb3/vsi1 pb4/vol2 pb5/vsi2 pb6/vol3 pb7/vsi3 avcc avr avss pc0/an0/sw1 pc1/an1/sw2 pc2/an2/sw3 pc3/an3 pc4/an4 pc5/an5 pc6/an6 pc7/an7 pd0/an8 vcc vss md2 md1 md0 pd1/an9 pd2/an10 pd3/an11 pd4/da1 pd5/da2 pd6/ppg2 p90/scl2 p91/sda2 p92/scl3 p93/sda3 p94/scl4 p95/sda4 p80/scl1 p81/sda1 p37/adtg p36 p35 p34 p33 p32 p31 p30 p27 p26 p25 p24 p23 p22 p21 x1 x0 vss vcc p20 p17 p16 p15 p14 p13 p12 p11 p10 p07/ksi7 p06/ksi6 p05/ksi5 p04/ksi4 p03/ksi3 p02/ksi2 p01/ksi1 p00/ksi0 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 lqfp-144 * : high current pins
mb90370/375 series 7 ?mb90f377 (top view) (fpt-144p-m12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 p40/psck0 p41/psda0 p42/psck1 p43/psda1 p44/psck2 p45/psda2 p46/clkrun p47/serirq p50/ga20 p51/lframe p52/lreset p53/lck p54/lad0 p55/lad1 p56/lad2 p57/lad3 rst vcc vss x0a x1a pa0/alr1 pa1/alr2 pa2/alr3 pa3/aco pa4/ofb1 pa5/ofb2 pa6/ofb3 cvcc cvrh1 cvrh2 cvrl cvss pb0/dcin pb1/dcin2 pb2/vol1 p77/ppg1 p76/ui3 p75/uo3 p74/uck3 p73/ui2 p72/uo2 p71/uck2 p70/ui1 p67/uo1 p66/uck1 p65/int5 p64/int4 p63/int3 p62/int2 p61/int1 p60/int0 pd7/ppg3 vss vcc pf7* pf6* pf5* pf4* pf3* pf2* pf1* pf0* pe7/to4 pe6/tin4 pe5/to3 pe4/tin3 pe3/to2 pe2/tin2 pe1/to1 pe0/tin1 p82/alert 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 pb3/vsi1 pb4/vol2 pb5/vsi2 pb6/vol3 pb7/vsi3 avcc avr avss pc0/an0/sw1 pc1/an1/sw2 pc2/an2/sw3 pc3/an3 pc4/an4 pc5/an5 pc6/an6 pc7/an7 pd0/an8 vcc vss md2 md1 md0 pd1/an9 pd2/an10 pd3/an11 pd4/da1 pd5/da2 pd6/ppg2 p90/scl2 p91/sda2 p92/scl3 p93/sda3 p94/scl4 p95/sda4 p80/scl1 p81/sda1 p37/adtg p36 p35 p34 p33 p32 p31 p30 p27 p26 p25 p24 p23 p22 p21 x1 x0 vss vcc p20 p17 p16 p15 p14 p13 p12 p11 p10 p07/ksi7 p06/ksi6 p05/ksi5 p04/ksi4 p03/ksi3 p02/ksi2 p01/ksi1 p00/ksi0 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 lqfp-144 * : high current pins
mb90370/375 series 8 n n n n pin description (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 128, 129 x0, x1 a oscillating main oscillation pins. 20, 21 x0a, x1a a oscillating sub-clock oscillation pins. 17 rst b reset input external reset input pin. 58, 57, 56 md0 to md2 c mode input input pin for operation mode specification. connect this pin directly to vcc or vss. 109 to 116 p00 to p07 d port input general-purpose i/o ports. ksi0 to ksi7 can be used as key-on wake-up interrupt input channel 0 to channel 7. input is enabled when 1 is set in eicr : en0 to en7 in standby mode. 117 to 124 p10 to p17 e general-purpose i/o ports. 125, 130 to 136 p20 to p27 e general-purpose i/o ports. 137 to 143 p30 to p36 e general-purpose i/o ports. 144 p37 e general-purpose i/o ports. adtg external trigger input pin (adtg) for the a/d converter. 1 p40 f general-purpose n-ch open-drain i/o port. psck0 serial clock i/o pin for ps/2 interface channel 0. this function is selected when ps/2 interface channel 0 is enabled. 2 p41 f general-purpose n-ch open-drain i/o port. psda0 serial data i/o pin for ps/2 interface channel 0. this function is selected when ps/2 interface channel 0 is enabled. 3 p42 f general-purpose n-ch open-drain i/o port. psck1 serial clock i/o pin for ps/2 interface channel 1. this function is selected when ps/2 interface channel 1 is enabled. 4 p43 f general-purpose n-ch open-drain i/o port. psda1 serial data i/o pin for ps/2 interface channel 1. this function is selected when ps/2 interface channel 1 is enabled. 5 p44 f general-purpose n-ch open-drain i/o port. psck2 serial clock i/o pin for ps/2 interface channel 2. this function is selected when ps/2 interface channel 2 is enabled. 6 p45 f general-purpose n-ch open-drain i/o port. psda2 serial data i/o pin for ps/2 interface channel 2. this function is selected when ps/2 interface channel 2 is enabled. 7 p46 g general-purpose n-ch open-drain i/o port. clkrun lpc clock status / restart request i/o pin for serial irq control- ler. this function is selected when serial irq and lpc clock restart request is enabled.
mb90370/375 series 9 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 8 p47 h port input general-purpose i/o port. serirq serial irq data i/o pin for serial irq controller. this function is selected when serial irq is enabled. 9 p50 h general-purpose i/o port. ga20 ga20 output for lpc interface. this function is selected when ga20 function is enabled. 10 p51 h general-purpose i/o port. lframe lframe input for lpc interface. this function is selected when lpc interface is enabled. 11 p52 h general-purpose i/o port. lreset reset input for lpc interface. this function is selected when lpc interface is enabled. 12 p53 h general-purpose i/o port. lck clock input for lpc interface. this function is selected when lpc interface is enabled. 13 to 16 p54 to p57 h general-purpose i/o ports. lad0 to lad3 address/data i/o for lpc interface. this function is selected when lpc interface is enabled. 93 to 98 p60 to p65 i general-purpose i/o ports. int0 to int5 can be used as dtp/external interrupt request input channel 0 to 5. input is enabled when 1 is set in enir : en0 to en5 in standby mode. 99 p66 i general-purpose i/o port. uck1 serial clock i/o pin for uart channel 1. this function is enabled when uart channel 1 enables clock output. 100 p67 i general-purpose i/o port. uo1 serial data output pin for uart channel 1. this function is enabled when uart channel 1 enables data output. 101 p70 i general-purpose i/o port. ui1 serial data input pin for uart channel 1. while uart channel 1 is operating for input, the input of this pin is used as required and must not be used for any other input. 102 p71 i general-purpose i/o port. uck2 serial clock i/o pin for uart channel 2. this function is enabled when uart channel 2 enables clock output.
mb90370/375 series 10 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 103 p72 i port input general-purpose i/o port. uo2 serial data output pin for uart channel 2. this function is enabled when uart channel 2 enables data output. 104 p73 i general-purpose i/o port. ui2 serial data input pin for uart channel 2. while uart channel 2 is operating for input, the input of this pin is used as required and must not be used for any other input. 105 p74 i general-purpose i/o port. uck3 serial clock i/o pin for uart channel 3. this function is enabled when uart channel 3 enables clock output. 106 p75 i general-purpose i/o port. uo3 serial data output pin for uart channel 3. this function is enabled when uart channel 3 enables data output. 107 p76 i general-purpose i/o port. ui3 serial data input pin for uart channel 3. while uart channel 3 is operating for input, the input of this pin is used as required and must not be used for any other input. 108 p77 i general-purpose i/o port. ppg1 output pin for ppg channel 1. this function is enabled when ppg channel 1 output is enabled. 71 p80 t general-purpose n-ch open-drain i/o port. scl1 serial clock i/o pin for multi-address i 2 c. 72 p81 t general-purpose n-ch open-drain i/o port. sda1 serial data i/o pin for multi-address i 2 c. 73 p82 j general-purpose n-ch open-drain i/o port. alert alert output pin for multi-address i 2 c. 65 p90 t general-purpose n-ch open-drain i/o port. scl2 serial clock i/o pin for bridge circuit. 66 p91 t general-purpose n-ch open-drain i/o port. sda2 serial data i/o pin for bridge circuit. 67 p92 t general-purpose n-ch open-drain i/o port. scl3 serial clock i/o pin for bridge circuit. 68 p93 t general-purpose n-ch open-drain i/o port. sda3 serial data i/o pin for bridge circuit.
mb90370/375 series 11 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 69 p94 t port input general-purpose n-ch open-drain i/o port. scl4 serial clock i/o pin for bridge circuit. 70 p95 t general-purpose n-ch open-drain i/o port. sda4 serial data i/o pin for bridge circuit. 22 to 24 pa0 to pa2 h general-purpose i/o ports. alr1 to alr3 alarm signal output when battery 1 to 3 run down in comparator circuit. 25 pa3 h general-purpose i/o port. aco ac power set signal output in comparator circuit. 26 to 28 pa4 to pa6 h general-purpose i/o ports. ofb1 to ofb3 battery 1 to 3 discharge control signal output in comparator circuit. 34, 35 pb0 to pb1 k comparator input general-purpose i/o ports. dcin to dcin2 ac power monitoring input in comparator circuit. 36 pb2 k general-purpose i/o ports. vol1 battery 1 power instantaneous interruption monitoring input in comparator circuit. 37 pb3 k general-purpose i/o ports. vsi1 battery 1 indicator monitoring input in comparator circuit. 38 pb4 k general-purpose i/o ports. vol2 battery 2 power instantaneous interruption monitoring input in comparator circuit. 39 pb5 k general-purpose i/o ports. vsi2 battery 2 indicator monitoring input in comparator circuit. 40 pb6 k general-purpose i/o ports. vol3 battery 3 power instantaneous interruption monitoring input in comparator circuit. 41 pb7 k general-purpose i/o ports. vsi3 battery 3 indicator monitoring input in comparator circuit. 45 to 47 pc0 to pc2 l comparator input or a/d input general-purpose i/o ports. sw1 to sw3 battery 1 to 3 mount / dismount detection input in comparator circuit. an0 to an2 a/d converter analog input pin 0 to 2. this function is enabled when the analog input specification is enabled (ader1) .
mb90370/375 series 12 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 48 to 52 pc3 to pc7 m a/d input general-purpose i/o ports. an3 to an7 a/d converter analog input pin 3 to 7. this function is enabled when the analog input specification is enabled (ader1) . 53, 59 to 61 pd0 to pd3 m general-purpose i/o ports. an8 to an11 a/d converter analog input pin 8 to 11. this function is enabled when the analog input specification is enabled (ader2) . 62 to 63 pd4 to pd5 n port input general-purpose i/o ports. da1 to da2 d/a converter analog output 1 to 2. this function is selected when d/a converter is enabled. 64, 92 pd6 to pd7 h general-purpose i/o port. ppg2 to ppg3 output pin for ppg channel 2 to 3. this function is selected when ppg channel 2 to 3 output is enabled. 74 pe0 o1 (o2 for mb90f377) general-purpose i/o port. seg0* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin1 external clock input pin for reload timer 1. 75 pe1 o1 (o2 for mb90f377) general-purpose i/o port. seg1* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. to1 event output pin for reload timer 1. 76 pe2 o1 (o2 for mb90f377) general-purpose i/o port. seg2* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin2 external clock input pin for reload timer 2. 77 pe3 o1 (o2 for mb90f377) general-purpose i/o port. seg3* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. to2 event output pin for reload timer 2. 78 pe4 o1 (o2 for mb90f377) general-purpose i/o port. seg4* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin3 external clock input pin for reload timer 3. 79 pe5 o1 (o2 for mb90f377) general-purpose i/o port. seg5* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. to3 event output pin for reload timer 3.
mb90370/375 series 13 (continued) *1 : it doesnt exist in mb90f377. *2 : they dont exist in mb90f377. pin no. pin name i/o circuit pin status during reset function lqfp-144 80 pe6 o1 (o2 for mb90f377) port input general-purpose i/o port. seg6* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin4 external clock input pin for reload timer 4. 81 pe7 o1 (o2 for mb90f377) general-purpose i/o port. seg7* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. to4 event output pin for reload timer 4. 82 pf0 p1 (p2 for mb90f377) general-purpose i/o port. seg8* 1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. 83 to 86 pf1 to pf4 p1 (p2 for mb90f377) general-purpose i/o port. com0 to com3* 2 com output pin for lcd controller/driver. this function is selected when lcd com output is enabled. 87 to 89 pf5 to pf7 q1 (q2 for mb90f377) power input general-purpose i/o port. v1 to v3* 2 power input pin for lcd controller/driver. this function is selected when external voltage divider is enabled. 42 av cc r power input vcc power input pin for analog circuits. 43 avr s vref+ input pin for the a/d converter. this voltage must not exceed vcc. vref- is fixed to avss. 44 av ss r vss power input pin for analog circuits. 29 cv cc r power input vcc power input pin for analog circuits. 30 cvrh1 r standard power input pin of the comparator. 31 cvrh2 r 32 cvrl r 33 cv ss r vss power input pin for analog circuits. 19, 55, 91, 127 vss C power input power (0 v) input pin. 18, 54, 90, 126 vcc C power (3.3 v) input pin.
mb90370/375 series 14 n n n n i/o circuit type (continued) type circuit remarks a main/sub clock (main/sub clock crystal oscillator) ? high-rate oscillation feedback resistor of approximately 1 m w ? low-rate oscillation feedback resistor of approximately 10 m w b ? hysteresis input ? pull-up resistor approximately 50 k w c ? hysteresis input d ? cmos output ? hysteresis input ? selectable pull-up resistor approximately 50 k w ?i ol = 4 ma e ? cmos output ? cmos input ? selectable pull-up resistor approximately 50 k w ?i ol = 4 ma f ? n-ch open-drain output ? hysteresis input ?i ol = 4 ma ? 5 v tolerant x1/x1a xout x0/x0a standby mode control n-ch p-ch p-ch n-ch r p-ch p-ch n-ch pout nout r pull-up control hysteresis input standby mode control p-ch p-ch n-ch pout nout r pull-up control cmos input standby mode control n-ch n-ch nout hysteresis input standby mode control
mb90370/375 series 15 (continued) type circuit remarks g ? n-ch open-drain output ? cmos input ?i ol = 4 ma h ? cmos output ? cmos input ?i ol = 4 ma i ? cmos output ? hysteresis input ?i ol = 4 ma j ? n-ch open-drain output ? cmos input ?i ol = 4 ma ? 5 v tolerant k ? cmos output ? cmos input ? comparator input ?i ol = 4 ma p-ch n-ch nout cmos input standby mode control p-ch n-ch nout pout cmos input standby mode control p-ch n-ch nout pout hysteresis input standby mode control n-ch n-ch nout standby mode control cmos input p-ch n-ch nout pout cmos input standby mode control + - comparator input
mb90370/375 series 16 (continued) type circuit remarks l ? cmos output ? cmos input ? comparator input ? a/d analog input ?i ol = 4 ma m ? cmos output ? cmos input ? a/d analog input ?i ol = 4 ma n ? cmos output ? cmos input ? d/a analog output ?i ol = 4 ma o1 ? cmos output ? cmos input ? segment output ?i ol = 4 ma p-ch n-ch nout pout cmos input standby mode control + - comparator input analog input p-ch n-ch nout pout cmos input standby mode control analog input p-ch n-ch nout pout cmos input standby mode control analog input p-ch n-ch nout pout cmos input standby mode control segment output
mb90370/375 series 17 (continued) type circuit remarks o2 ? cmos output ? cmos input ?i ol = 4 ma p1 ? cmos output ? cmos input ? segment output ?i ol = 12 ma p2 ? cmos output ? cmos input ?i ol = 12 ma q1 ? cmos output ? cmos input ? lcd driving power supply ?i ol = 12 ma q2 ? cmos output ? cmos input ?i ol = 12 ma p-ch n-ch nout pout cmos input standby mode control p-ch n-ch nout pout cmos input standby mode control segment output p-ch n-ch nout pout cmos input standby mode control p-ch n-ch nout pout cmos input standby mode control lcd driving power supply p-ch n-ch nout pout cmos input standby mode control
mb90370/375 series 18 (continued) type circuit remarks r ? power supply input protection circuit s ? a/d converter reference voltage (avr) input pin with protection circuit t ? n-ch open-drain output ? cmos input ?i ol = 4 ma ? 5 v tolerant p-ch n-ch in p-ch n-ch in analog input enable analog input enable n-ch n-ch nout cmos input standby mode control
mb90370/375 series 19 n n n n handling devices ? be sure that the maximum rated voltage is not exceeded (latch-up prevention) . a latch-up may occur on a cmos ic if a voltage higher than v cc or lower than v ss is applied to an input or output pin other than medium-to-high voltage pins. a latch-up may also occur if a voltage higher than the rating is applied between v cc and v ss . a latch-up causes a rapid increase in the power supply current, which can result in thermal damage to an element. take utmost care that the maximum rated voltage is not exceeded. when turning the power on or off to analog circuits, be sure that the analog supply voltages (av cc , cv cc , avr, cvrh1, cvrh2 and cvrl) and analog input voltage do not exceed the digital supply voltage (v cc ) . ? stabilize the supply voltages even within the operation guarantee range of the v cc supply voltage, a malfunction can be caused if the supply voltage undergoes a rapid change. for voltage stabilization guidelines, the v cc ripple fluctuations (p-p value) at commercial frequencies (50 hz to 60 hz) should be suppressed to 10 % or less of the reference v cc value. during a momentary change such as when switching a supply voltage, voltage fluctuations should also be suppressed so that the transient fluctuation rate is 0.1 v/ms or less. ?power-on to prevent a malfunction in the built-in voltage drop circuit, secure 50 m s (between 0.2 v and 1.8 v) or more for the voltage rise time during power-on. ? treatment of unused input pins an unused input pin may cause a malfunction if it is left open. every unused input pin should be pulled up or down. ? treatment of a/d converter, d/a converter and comparator power pin when the a/d converter, d/a converter and comparator is not used, connect the pins as follows : av cc = cv cc = v cc , av ss = avr = cv ss = cvrl = cvrh1 = cvrh2 = v ss . ? notes on external clock when an external clock is used, the oscillation stabilization wait time is required at power-on reset or at cancellation of sub-clock mode or stop mode. as shown in diagram below, when an external clock is used, connect only the x0 pin and leave the x1 pin open. ? power supply pins when a device has two or more v cc or v ss pins, the pins that should have equal potential are connected within the device in order to prevent a latch-up or other malfunction. to reduce extraneous emission, to prevent a malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current rating, connect all these power supply pins to an external power supply and ground them. the current source should be connected to the v cc and v ss pins of the device with minimum impedance. it is recommended that a bypass capacitor of about 0.1 m f be connected near the terminals between v cc and v ss . open mb90370/375 series x0 x1
mb90370/375 series 20 ? analog power-on sequence of a/d converter, d/a converter and comparator the power to the a/d converter, d/a converter and comparator (av cc , cv cc , avr, cvrh1, cvrh2 and cvrl) and analog inputs (an0 to an11, vol1 to vol3, vsi1 to vsi3, sw1 to sw3, dcin and dcin2) must be turned on after the power to the digital circuits (v cc ) is turned on. when turning off the power, turn off the power to the digital circuits (v cc ) after turning off the power to the a/d converter, d/a converter, comparator and analog inputs. when the power is turned on or off, avr should not exceed av cc . and cvrh1, cvrh2 and cvrl should not exceed cv cc . also, when a pin that is used for a/d analog input is used as an input port, the input voltage should not exceed av cc . and when comparator analog input is also used as an input port, the input voltage should not exceed cv cc . (the power to the analog circuits and the power to the digital circuits can be simultaneously turned on or off.) ? caution on operations during pll clock mode if the pll clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed.
mb90370/375 series 21 n n n n block diagram ? mb90372/f372/v370 clock control circuit reset circuit (watchdog timer) interrupt controller vss x 4, vcc x 4, md0-2, avcc, avss, cvcc, cvss other pins delayed interrupt generator i 2 c bus (multi-address) i 2 c bus bridge circuit n-ch open-drain i/o port 8, 9 cmos i/o port a, b cmos i/o port c, d cmos i/o port e, f battery select circuit voltage comparator a/d converter (8/10 bit) 16-bit ppg (ch2, 3) 16-bit reload timer (ch1, 2, 3, 4) d/a converter f 2 mc-16lx bus comparator timebase timer 8 8 8 8 8 6 6 3 8 7 6 12 2 6 2 7 cmos i/o port 0, 1, 2, 3* cmos i/o port 5 dtp/external interrupt 16-bit ppg (ch1) cmos i/o port 6, 7 ram rom rom correction rom mirroring uart (ch1, 2, 3) 3ch ps/2 interface serial irq (6 channels) lpc interface gatea20 control upi (ch0, 1, 2, 3) bus interface n-ch open-drain i/o port 4 (p47 is cmos i/o port) key-on wake-up interrupt x0, x0a x1, x1a rst p00/ksi0 to p07/ksi7 p10 to p17 p20 to p27 p40/psck0 p41/psda0 p42/psck1 p43/psda1 p44/psck2 p45/psda2 p46/clkrun p47/serirq p50/ga20 p51/lframe p52/lreset p53/lck p54/lad0 p55/lad1 p56/lad2 p57/lad3 p66/uck1 p67/uo1 p70/ui1 p71/uck2 p72/uo2 p73/ui2 p74/uck3 p75/uo3 p76/ui3 p77/ppg1 p60/int0 to p65/int5 p30 to p36 p37/adtg cpu f 2 mc-16lx series core p80/scl1 p81/sda1 p82/alert p90/scl2 p91/sda2 p92/scl3 p93/sda3 p94/scl4 p95/sda4 pa0/alr1 to pa2/alr3 pa3/aco pa4/ofb1 to pa6/ofb3 pb0/dcin pb1/dcin2 pb2/vol1 pb3/vsi1 pb4/vol2 pb5/vsi2 pb6/vol3 pb7/vsi3 pc0/an0/sw1 pc1/an1/sw2 pc2/an2/sw3 pc3/an3 to pc7/an7 pd0/an8 to pd3/an11 pd4/da1 pd5/da2 pd6/ppg2 pd7/ppg3 pe0/tin1 pe1/to1 pe2/tin2 pe3/to2 pe4/tin3 pe5/to3 pe6/tin4 pe7/to4 pf0 pf1 to pf4 pf5 to pf7 cvrh1, cvrh2, cvrl avr * : p00 to p07, p10 to p17, p20 to p27, p30 to p37 : with registers that can be used as input pull-up resistors note: pf0 to pf7 : high current pins
mb90370/375 series 22 ?mb90f377 clock control circuit reset circuit (watchdog timer) interrupt controller vss x 4, vcc x 4, md0-2, avcc, avss, cvcc, cvss other pins delayed interrupt generator i 2 c bus (multi-address) i 2 c bus bridge circuit n-ch open-drain i/o port 8, 9 cmos i/o port a, b cmos i/o port c, d cmos i/o port e, f battery select circuit voltage comparator a/d converter (8/10 bit) 16-bit ppg (ch2, 3) 16-bit reload timer (ch1, 2, 3, 4) d/a converter f 2 mc-16lx bus comparator timebase timer 8 8 8 8 8 6 6 3 8 7 6 12 2 6 2 7 cmos i/o port 0, 1, 2, 3* cmos i/o port 5 dtp/external interrupt 16-bit ppg (ch1) cmos i/o port 6, 7 ram rom rom correction rom mirroring uart (ch1, 2, 3) 3ch ps/2 interface serial irq (6 channels) lpc interface gatea20 control upi (ch0, 1, 2, 3) bus interface n-ch open-drain i/o port 4 (p47 is cmos i/o port) key-on wake-up interrupt x0, x0a x1, x1a rst p00/ksi0 to p07/ksi7 p10 to p17 p20 to p27 p40/psck0 p41/psda0 p42/psck1 p43/psda1 p44/psck2 p45/psda2 p46/clkrun p47/serirq p50/ga20 p51/lframe p52/lreset p53/lck p54/lad0 p55/lad1 p56/lad2 p57/lad3 p66/uck1 p67/uo1 p70/ui1 p71/uck2 p72/uo2 p73/ui2 p74/uck3 p75/uo3 p76/ui3 p77/ppg1 p60/int0 to p65/int5 p30 to p36 p37/adtg cpu f 2 mc-16lx series core p80/scl1 p81/sda1 p82/alert p90/scl2 p91/sda2 p92/scl3 p93/sda3 p94/scl4 p95/sda4 pa0/alr1 to pa2/alr3 pa3/aco pa4/ofb1 to pa6/ofb3 pb0/dcin pb1/dcin2 pb2/vol1 pb3/vsi1 pb4/vol2 pb5/vsi2 pb6/vol3 pb7/vsi3 pc0/an0/sw1 pc1/an1/sw2 pc2/an2/sw3 pc3/an3 to pc7/an7 pd0/an8 to pd3/an11 pd4/da1 pd5/da2 pd6/ppg2 pd7/ppg3 pe0/tin1 pe1/to1 pe2/tin2 pe3/to2 pe4/tin3 pe5/to3 pe6/tin4 pe7/to4 pf0 pf1 to pf4 pf5 to pf7 cvrh1, cvrh2, cvrl avr * : p00 to p07, p10 to p17, p20 to p27, p30 to p37 : with registers that can be used as input pull-up resistors note: pf0 to pf7 : high current pins
mb90370/375 series 23 n n n n memory map * : the mb90v370 does not contain rom. assume that the development tool uses these area for its rom decode areas. note : rom data in the ff bank can be seen as an image in the higher 00 bank to validate the small model c compiler. because addresses of the 16 low-order bits in the ff bank are the same, the table in rom can be referenced without the far specification. for example, when 00c000 h is accessed, the contents of rom at ffc000 h are actually accessed. the rom area in the ff bank exceeds 48 kilobytes, and all areas cannot be seen as images in the 00 bank. because rom data from ff4000 h to ffffff h is seen as an image at 004000 h to 00ffff h , the rom data table should be stored in the area from ff4000 h to ffffff h . model address #1 address #2 address #3 mb90372 ff0000 h 004000 h 001900 h mb90f372/f377 ff0000 h 004000 h 001900 h mb90v370 ff0000 h * 004000 h * 003fc0 h single-chip mode (with rom mirroring function) rom area peripheral area peripheral area register rom area (ff bank image) ram area ffffff h address #1 fc0000 h 010000 h address #2 004000 h 003fc0 h address #3 000100 h 0000f8 h 000000 h : internal access memory : access not allowed
mb90370/375 series 24 n n n n f 2 mc-16lx cpu programming model ? dedicated registers al accumulator (a) ah usp ssp ps pc user stack pointer (usp) system stack pointer (ssp) processor status (ps) program counter (pc) dpr pcb dtb usb ssb adb direct page register (dpr) program bank register (pcb) data bank register (dtb) user stack bank register (usb) system stack bank register (ssb) additional data bank register (adb) 8 bits 16 bits 32 bits
mb90370/375 series 25 ? general-purpose registers ? processor status (ps) dedicated register ram accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register internal bus general-purpose register cpu ram 15 ps ? istn b4 b3 b2 b1 b0 00000 ilm2 ilm1 ilm0 000 z v c : ccr : rp : ilm 76543210 ? 0 1xxxxx ilm rp ccr 000 00000 -01xxxxx 1312 8 7 0 default value default value default value default value - : not used x : undefined
mb90370/375 series 26 n n n n i/o map (continued) address abbrevia- tion register byte access word access resource name initial value 000000 h pdr0 port 0 data register r/w r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w r/w port 4 x1111111 b 000005 h pdr5 port 5 data register r/w r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w r/w port 7 xxxxxxxx b 000008 h pdr8 port 8 data register r/w r/w port 8 -----111 b 000009 h pdr9 port 9 data register r/w r/w port 9 --111111 b 00000a h pdra port a data register r/w r/w port a -xxxxxxx b 00000b h pdrb port b data register r/w r/w port b xxxxxxxx b 00000c h pdrc port c data register r/w r/w port c xxxxxxxx b 00000d h pdrd port d data register r/w r/w port d xxxxxxxx b 00000e h pdre port e data register r/w r/w port e xxxxxxxx b 00000f h pdrf port f data register r/w r/w port f xxxxxxxx b 000010 h ddr0 port 0 direction register r/w r/w port 0 00000000 b 000011 h ddr1 port 1 direction register r/w r/w port 1 00000000 b 000012 h ddr2 port 2 direction register r/w r/w port 2 00000000 b 000013 h ddr3 port 3 direction register r/w r/w port 3 00000000 b 000014 h ddr4 port 4 direction register r/w r/w port 4 0------- b 000015 h ddr5 port 5 direction register r/w r/w port 5 00000000 b 000016 h ddr6 port 6 direction register r/w r/w port 6 00000000 b 000017 h ddr7 port 7 direction register r/w r/w port 7 00000000 b 000018 h pgdr parity generator data register r/w r/w parity generator xxxxxxxx b 000019 h pgcsr parity generator control status register r/w r/w x------0 b 00001a h ddra port a direction register r/w r/w port a -0000000 b 00001b h ddrb port b direction register r/w r/w port b 00000000 b 00001c h ddrc port c direction register r/w r/w port c 00000000 b 00001d h ddrd port d direction register r/w r/w port d 00000000 b 00001e h ddre port e direction register r/w r/w port e 00000000 b 00001f h ddrf port f direction register r/w r/w port f 00000000 b
mb90370/375 series 27 (continued) address abbrevia- tion register byte access word access resource name initial value 000020 h smr1 serial mode register 1 r/w r/w uart1 00000-00 b 000021 h scr1 serial control register 1 r/w r/w 00000100 b 000022 h sidr1/ sodr1 input data register 1 / output data register 1 r/w r/w xxxxxxxx b 000023 h ssr1 serial status register 1 r/w r/w 00001000 b 000024 h m2cr1 mode 2 control register 1 r/w r/w ----1000 b 000025 h cdcr1 clock division control register 1 r/w r/w communication prescaler 1 0---0000 b 000026 h enir interrupt / dtp enable register r/w r/w dtp/external interrupt --000000 b 000027 h eirr interrupt / dtp cause register r/w r/w --xxxxxx b 000028 h elvr request level setting register r/w r/w 00000000 b 000029 h r/w r/w ----0000 b 00002a h ader1 analog input enable register 1 r/w r/w port c, a/d 11111111 b 00002b h ader2 analog input enable register 2 r/w r/w port d, a/d ----1111 b 00002c h brsr bridge circuit selection register r/w r/w bridge circuit --000000 b 00002d h adc0 a/d control register r/w r/w 8/10-bit a/d converter 00000000 b 00002e h adcr0 a/d data register r r xxxxxxxx b 00002f h adcr1 r/w r/w 00000-xx b 000030 h adcs0 a/d control status register r/w r/w 00-------- b 000031 h adcs1 r/w r/w 00000000 b 000032 h sicrl serial interrupt request register r/w r/w serial irq 00000000 b 000033 h sicrh serial interrupt control register r/w r/w 00000000 b 000034 h sifr1 serial interrupt frame number register 1 r/w r/w --000000 b 000035 h sifr2 serial interrupt frame number register 2 r/w r/w --000000 b 000036 h sifr3 serial interrupt frame number register 3 r/w r/w --000000 b 000037 h sifr4 serial interrupt frame number register 4 r/w r/w --000000 b
mb90370/375 series 28 (continued) address abbrevia- tion register byte access word access resource name initial value 000038 h pdcrl1 ppg1 down counter register ? r 16-bit ppg timer (ch1) 11111111 b 000039 h pdcrh1 ? r 11111111 b 00003a h pcsrl1 ppg1 period setting register ? w xxxxxxxx b 00003b h pcsrh1 ? w xxxxxxxx b 00003c h pdutl1 ppg1 duty setting register ? w xxxxxxxx b 00003d h pduth1 ? w xxxxxxxx b 00003e h pcntl1 ppg1 control status register r/w r/w --000000 b 00003f h pcnth1 r/w r/w 00000000 b 000040 h pdcrl2 ppg2 down counter register ? r 16-bit ppg timer (ch2) 11111111 b 000041 h pdcrh2 ? r 11111111 b 000042 h pcsrl2 ppg2 period setting register ? w xxxxxxxx b 000043 h pcsrh2 ? w xxxxxxxx b 000044 h pdutl2 ppg2 duty setting register ? w xxxxxxxx b 000045 h pduth2 ? w xxxxxxxx b 000046 h pcntl2 ppg2 control status register r/w r/w --000000 b 000047 h pcnth2 r/w r/w 00000000 b 000048 h pdcrl3 ppg3 down counter register ? r 16-bit ppg timer (ch3) 11111111 b 000049 h pdcrh3 ? r 11111111 b 00004a h pcsrl3 ppg3 period setting register ? w xxxxxxxx b 00004b h pcsrh3 ? w xxxxxxxx b 00004c h pdutl3 ppg3 duty setting register ? w xxxxxxxx b 00004d h pduth3 ? w xxxxxxxx b 00004e h pcntl3 ppg3 control status register r/w r/w --000000 b 00004f h pcnth3 r/w r/w 00000000 b 000050 h pscr0 ps/2 interface control register 0 r/w r/w 3-channel ps/2 interface 0--00000 b 000051 h pssr0 ps/2 interface status register 0 r/w r/w 00000000 b 000052 h pscr1 ps/2 interface control register 1 r/w r/w 0--00000 b 000053 h pssr1 ps/2 interface status register 1 r/w r/w 00000000 b 000054 h pscr2 ps/2 interface control register 2 r/w r/w 0--00000 b 000055 h pssr2 ps/2 interface status register 2 r/w r/w 00000000 b 000056 h psdr0 ps/2 interface data register 0 r/w r/w 00000000 b 000057 h psdr1 ps/2 interface data register 1 r/w r/w 00000000 b 000058 h psdr2 ps/2 interface data register 2 r/w r/w 00000000 b 000059 h psmr ps/2 interface mode register r/w r/w ----0000 b
mb90370/375 series 29 (continued) address abbrevia- tion register byte access word access resource name initial value 00005a h dat0 d/a converter data register 0 r/w r/w d/a converter xxxxxxxx b 00005b h dat1 d/a converter data register 1 r/w r/w xxxxxxxx b 00005c h dacr0 d/a control register 0 r/w r/w -------0 b 00005d h dacr1 d/a control register 1 r/w r/w -------0 b 00005e h upal1 upi1 address register (lower) r/w r/w lpc interface xxxxxxxx b 00005f h upah1 upi1 address register (upper) r/w r/w xxxxxxxx b 000060 h upal2 upi2 address register (lower) r/w r/w xxxxxxxx b 000061 h upah2 upi2 address register (upper) r/w r/w xxxxxxxx b 000062 h upal3 upi3 address register (lower) r/w r/w xxxxxxxx b 000063 h upah3 upi3 address register (upper) r/w r/w xxxxxxxx b 000064 h upcl upi control register (lower) r/w r/w 00000000 b 000065 h upch upi control register (upper) r/w r/w -000-000 b 000066 h updi0/ updo0 upi0 data input register / data output register r/w r/w xxxxxxxx b 000067 h ups0 upi0 status register r/w r/w 00000000 b 000068 h updi1/ updo1 upi1 data input register / data output register r/w r/w xxxxxxxx b 000069 h ups1 upi1 status register r/w r/w 00000000 b 00006a h updi2/ updo2 upi2 data input register / data output register r/w r/w xxxxxxxx b 00006b h ups2 upi2 status register r/w r/w 00000000 b 00006c h updi3/ updo3 upi3 data input register / data output register r/w r/w xxxxxxxx b 00006d h ups3 upi3 status register r/w r/w 00000000 b 00006e h lcr lpc control register r/w r/w -----000 b 00006f h romm rom mirroring function selection register ww rom mirroring function ------01 b 000070 h tmcsrl1 timer control status register ch1 (lower) r/w r/w 16-bit reload timer (ch1) 00000000 b 000071 h tmcsrh1 timer control status register ch1 (upper) r/w r/w ----0000 b 000072 h tmr1/ tmrd1 16-bit timer/reload register ch1 ? r/w xxxxxxxx b 000073 h ? r/w xxxxxxxx b
mb90370/375 series 30 (continued) address abbrevia- tion register byte access word access resource name initial value 000074 h tmcsrl2 timer control status register ch2 (lower) r/w r/w 16-bit reload timer (ch2) 00000000 b 000075 h tmcsrh2 timer control status register ch2 (upper) r/w r/w ----0000 b 000076 h tmr2/ tmrd2 16-bit timer/reload register ch2 ? r/w xxxxxxxx b 000077 h ? r/w xxxxxxxx b 000078 h tmcsrl3 timer control status register ch3 (lower) r/w r/w 16-bit reload timer (ch3) 00000000 b 000079 h tmcsrh3 timer control status register ch3 (upper) r/w r/w ----0000 b 00007a h tmr3/ tmrd3 16-bit timer/reload register ch3 ? r/w xxxxxxxx b 00007b h ? r/w xxxxxxxx b 00007c h tmcsrl4 timer control status register ch4 (lower) r/w r/w 16-bit reload timer (ch4) 00000000 b 00007d h tmcsrh4 timer control status register ch4 (upper) r/w r/w ----0000 b 00007e h tmr4/ tmrd4 16-bit timer/reload register ch4 ? r/w xxxxxxxx b 00007f h ? r/w xxxxxxxx b 000080 h ibcrl i 2 c bus control register (lower) r/w r/w i 2 c ----0000 b 000081 h ibcrh i 2 c bus control register (upper) r/w r/w 00000000 b 000082 h ibsrl i 2 c bus status register (lower) r r 00000000 b 000083 h ibsrh i 2 c bus status register (upper) r/w r/w --000000 b 000084 h idar i 2 c data register r/w r/w xxxxxxxx b 000085 h iadr i 2 c address register r/w r/w -xxxxxxx b 000086 h iccr i 2 c clock control register r/w r/w 0-000000 b 000087 h itcr i 2 c timeout control register r/w r/w -0-00000 b 000088 h itoc i 2 c timeout clock register r/w r/w 00000000 b 000089 h itod i 2 c timeout data register r/w r/w 00000000 b 00008a h isto i 2 c slave timeout register r/w r/w 00000000 b 00008b h imto i 2 c master timeout register r/w r/w 00000000 b 00008c h rdr0 port 0 pull-up resistor setting register r/w r/w port 0 00000000 b 00008d h rdr1 port 1 pull-up resistor setting register r/w r/w port 1 00000000 b 00008e h rdr2 port 2 pull-up resistor setting register r/w r/w port 2 00000000 b 00008f h rdr3 port 3 pull-up resistor setting register r/w r/w port 3 00000000 b
mb90370/375 series 31 (continued) address abbrevia- tion register byte access word access resource name initial value 000090 h to 9d h prohibited area 00009e h pacsr program address detect control status register r/w r/w rom correction ----0000 b 00009f h dirr delayed interrupt cause / clear register r/w r/w delayed interrupt -------0 b 0000a0 h lpmcr low-power consumption mode register r/w r/w low-power consumption control register 00011000 b 0000a1 h ckscr clock selection register r/w r/w 11111100 b 0000a2 h to a7 h prohibited area 0000a8 h wdtc watchdog control register r/w r/w watchdog timer x-xxx111 b 0000a9 h tbtc timebase timer control register r/w r/w timebase timer 1--00100 b 0000aa h wtc watch timer control register r/w r/w watch timer 10001000 b 0000ab h prohibited area 0000ac h eicr wake-up interrupt control register r/w r/w wake-up interrupt 00000000 b 0000ad h eifr wake-up interrupt flag register r/w r/w -------0 b 0000ae h fmcs flash memory control status register r/w r/w flash memory interface circuit 00010000 b 0000af h prohibited area 0000b0 h icr00 interrupt control register 00 r/w r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w r/w 00000111 b 0000b2 h icr02 interrupt control register 02 r/w r/w 00000111 b 0000b3 h icr03 interrupt control register 03 r/w r/w 00000111 b 0000b4 h icr04 interrupt control register 04 r/w r/w 00000111 b 0000b5 h icr05 interrupt control register 05 r/w r/w 00000111 b 0000b6 h icr06 interrupt control register 06 r/w r/w 00000111 b 0000b7 h icr07 interrupt control register 07 r/w r/w 00000111 b 0000b8 h icr08 interrupt control register 08 r/w r/w 00000111 b 0000b9 h icr09 interrupt control register 09 r/w r/w 00000111 b 0000ba h icr10 interrupt control register 10 r/w r/w 00000111 b
mb90370/375 series 32 (continued) address abbrevia- tion register byte access word access resource name initial value 0000bb h icr11 interrupt control register 11 r/w r/w interrupt controller 00000111 b 0000bc h icr12 interrupt control register 12 r/w r/w 00000111 b 0000bd h icr13 interrupt control register 13 r/w r/w 00000111 b 0000be h icr14 interrupt control register 14 r/w r/w 00000111 b 0000bf h icr15 interrupt control register 15 r/w r/w 00000111 b 0000c0 h mbcrl mi 2 c bus control register (lower) r/w r/w mi 2 c ----0000 b 0000c1 h mbcrh mi 2 c bus control register (upper) r/w r/w 00000000 b 0000c2 h mbsrl mi 2 c bus status register (lower) r r 00000000 b 0000c3 h mbsrh mi 2 c bus status register (upper) r/w r/w --000000 b 0000c4 h mdar mi 2 c data register r/w r/w xxxxxxxx b 0000c5 h malr mi 2 c alert register r/w r/w ----0000 b 0000c6 h madr1 mi 2 c address register 1 r/w r/w -xxxxxxx b 0000c7 h madr2 mi 2 c address register 2 r/w r/w -xxxxxxx b 0000c8 h madr3 mi 2 c address register 3 r/w r/w -xxxxxxx b 0000c9 h madr4 mi 2 c address register 4 r/w r/w -xxxxxxx b 0000ca h madr5 mi 2 c address register 5 r/w r/w -xxxxxxx b 0000cb h madr6 mi 2 c address register 6 r/w r/w -xxxxxxx b 0000cc h mccr mi 2 c clock control register r/w r/w 0-000000 b 0000cd h mtcr mi 2 c timeout control register r/w r/w -0-00000 b 0000ce h mtoc mi 2 c timeout clock register r/w r/w 00000000 b 0000cf h mtod mi 2 c timeout data register r/w r/w 00000000 b 0000d0 h msto mi 2 c slave timeout register r/w r/w 00000000 b 0000d1 h mmto mi 2 c master timeout register r/w r/w 00000000 b 0000d2 h smr2 serial mode register 2 r/w r/w uart2 00000-00 b 0000d3 h scr2 serial control register 2 r/w r/w 00000100 b 0000d4 h sidr2/ sodr2 input data register 2 / output data register 2 r/w r/w xxxxxxxx b 0000d5 h ssr2 status register 2 r/w r/w 00001000 b 0000d6 h m2cr2 mode 2 control register 2 r/w r/w ----1000 b 0000d7 h cdcr2 clock division control register 2 r/w r/w communication prescaler 2 0---0000 b
mb90370/375 series 33 (continued) address abbrevia- tion register byte access word access resource name initial value 0000d8 h cocrl comparator control register (lower) r/w r/w voltage comparator --000000 b 0000d9 h cocrh comparator control register (upper) r/w r/w 00011111 b 0000da h cosrl1 comparator status register 1 (lower) r/w r/w 00000000 b 0000db h cosrh1 comparator status register 1 (upper) r/w r/w --000000 b 0000dc h cicrl comparator interrupt control register (lower) r/w r/w 00000000 b 0000dd h cicrh comparator interrupt control register (upper) r/w r/w --000000 b 0000de h cosrl2 comparator status register 2 (lower) r r xxxxxxxx b 0000df h cosrh2 comparator status register 2 (upper) r r --xxxxxx b 0000e0 h cier comparator input enable register r/w r/w ---11111 b 0000e1 h bdr bit data register r/w r/w bit decoder ----xxxx b 0000e2 h brrl bit result register (lower) r r xxxxxxxx b 0000e3 h brrh bit result register (upper) r r xxxxxxxx b 0000e4 h smr3 serial mode register 3 r/w r/w uart3 00000-00 b 0000e5 h scr3 serial control register 3 r/w r/w 00000100 b 0000e6 h sidr3/ sodr3 input data register 3 / output data register 3 r/w r/w xxxxxxxx b 0000e7 h ssr3 status register 3 r/w r/w 00001000 b 0000e8 h m2cr3 mode 2 control register 3 r/w r/w ----1000 b 0000e9 h cdcr3 clock division control register 3 r/w r/w communication prescaler 3 0---0000 b 0000ea h pdl3 port 3 data latch register r/w r/w port 3 data latch 00000000 b 0000eb h to ed h prohibited area 0000ee h lcrl* 1 lcd control register 0* 2 r/w r/w lcd controller / driver 00010000 b 0000ef h lcrh* 1 lcd control register 1* 2 r/w r/w 00000000 b 0000f0 h to f4 h vram* 1 lcd display ram* 2 r/w ? xxxxxxxx b 0000f5 h to f7 h prohibited area 0000f8 h to ff h external area
mb90370/375 series 34 (continued) address abbrevia- tion register byte access word access resource name initial value 001ff0 h padr0 program address detection register 0 r/w r/w rom correction xxxxxxxx b 001ff1 h program address detection register 1 r/w r/w xxxxxxxx b 001ff2 h program address detection register 2 r/w r/w xxxxxxxx b 001ff3 h padr1 program address detection register 3 r/w r/w xxxxxxxx b 001ff4 h program address detection register 4 r/w r/w xxxxxxxx b 001ff5 h program address detection register 5 r/w r/w xxxxxxxx b 003fc0 h udrl0 up data register 0 (lower) r/w r/w lpc data buffer array xxxxxxxx b 003fc1 h udrh0 up data register 0 (upper) r/w r/w xxxxxxxx b 003fc2 h udrl1 up data register 1 (lower) r/w r/w xxxxxxxx b 003fc3 h udrh1 up data register 1 (upper) r/w r/w xxxxxxxx b 003fc4 h udrl2 up data register 2 (lower) r/w r/w xxxxxxxx b 003fc5 h udrh2 up data register 2 (upper) r/w r/w xxxxxxxx b 003fc6 h udrl3 up data register 3 (lower) r/w r/w xxxxxxxx b 003fc7 h udrh3 up data register 3 (upper) r/w r/w xxxxxxxx b 003fc8 h udrl4 up data register 4 (lower) r/w r/w xxxxxxxx b 003fc9 h udrh4 up data register 4 (upper) r/w r/w xxxxxxxx b 003fca h udrl5 up data register 5 (lower) r/w r/w xxxxxxxx b 003fcb h udrh5 up data register 5 (upper) r/w r/w xxxxxxxx b 003fcc h udrl6 up data register 6 (lower) r/w r/w xxxxxxxx b 003fcd h udrh6 up data register 6 (upper) r/w r/w xxxxxxxx b 003fce h udrl7 up data register 7 (lower) r/w r/w xxxxxxxx b 003fcf h udrh7 up data register 7 (upper) r/w r/w xxxxxxxx b 003fd0 h udrl8 up data register 8 (lower) r/w r/w xxxxxxxx b 003fd1 h udrh8 up data register 8 (upper) r/w r/w xxxxxxxx b 003fd2 h udrl9 up data register 9 (lower) r/w r/w xxxxxxxx b 003fd3 h udrh9 up data register 9 (upper) r/w r/w xxxxxxxx b
mb90370/375 series 35 (continued) address abbrevia- tion register byte access word access resource name initial value 003fd4 h udrla up data register a (lower) r/w r/w lpc data buffer array xxxxxxxx b 003fd5 h udrha up data register a (upper) r/w r/w xxxxxxxx b 003fd6 h udrlb up data register b (lower) r/w r/w xxxxxxxx b 003fd7 h udrhb up data register b (upper) r/w r/w xxxxxxxx b 003fd8 h udrlc up data register c (lower) r/w r/w xxxxxxxx b 003fd9 h udrhc up data register c (upper) r/w r/w xxxxxxxx b 003fda h udrld up data register d (lower) r/w r/w xxxxxxxx b 003fdb h udrhd up data register d (upper) r/w r/w xxxxxxxx b 003fdc h udrle up data register e (lower) r/w r/w xxxxxxxx b 003fdd h udrhe up data register e (upper) r/w r/w xxxxxxxx b 003fde h udrlf up data register f (lower) r/w r/w xxxxxxxx b 003fdf h udrhf up data register f (upper) r/w r/w xxxxxxxx b 003fe0 h dndl0 down data register 0 (lower) r r xxxxxxxx b 003fe1 h dndh0 down data register 0 (upper) r r xxxxxxxx b 003fe2 h dndl1 down data register 1 (lower) r r xxxxxxxx b 003fe3 h dndh1 down data register 1 (upper) r r xxxxxxxx b 003fe4 h dndl2 down data register 2 (lower) r r xxxxxxxx b 003fe5 h dndh2 down data register 2 (upper) r r xxxxxxxx b 003fe6 h dndl3 down data register 3 (lower) r r xxxxxxxx b 003fe7 h dndh3 down data register 3 (upper) r r xxxxxxxx b 003fe8 h dndl4 down data register 4 (lower) r r xxxxxxxx b 003fe9 h dndh4 down data register 4 (upper) r r xxxxxxxx b 003fea h dndl5 down data register 5 (lower) r r xxxxxxxx b 003feb h dndh5 down data register 5 (upper) r r xxxxxxxx b 003fec h dndl6 down data register 6 (lower) r r xxxxxxxx b 003fed h dndh6 down data register 6 (upper) r r xxxxxxxx b 003fee h dndl7 down data register 7 (lower) r r xxxxxxxx b 003fef h dndh7 down data register 7 (upper) r r xxxxxxxx b 003ff0 h dbaal data buffer array address register (lower) r/w r/w xxxxxxxx b 003ff1 h dbaah data buffer array address register (upper) r/w r/w xxxxxxxx b 003ff2 h to 003fff h prohibited area
mb90370/375 series 36 ? meaning of abbreviations used for reading and writing ? explanation of initial values ? instruction using io addressing e.g. mov a, io, is not supported for registers area 003fc0 h to 003fff h . *1 : it doesnt exist in mb90f377. *2 : prohibited area in mb90f377. r/w : read and write enabled r : read-only w : write-only 0 : the bit is initialized to 0. 1 : the bit is initialized to 1. x : the initial value of the bit is undefined. - : the bit is not used. its initial value is undefined.
mb90370/375 series 37 n n n n interrupt factors, interrupt vectors, interrupt control register interrupt cause ei 2 os support interrupt vector interrupt control register priority*2 number address icr address reset x #08 08 h ffffdc h ?? high low int9 instruction x #09 09 h ffffd8 h ?? exception processing x #10 0a h ffffd4 h ?? a/d converter conversion termination #11 0b h ffffd0 h icr00 0000b0 h *1 timebase timer #12 0c h ffffcc h upi0 ibf / lpc reset #13 0d h ffffc8 h icr01 0000b1 h *1 upi1 ibf #14 0e h ffffc4 h upi2 ibf #15 0f h ffffc0 h icr02 0000b2 h *1 upi3 ibf #16 10 h ffffbc h dtp/ext. interrupt channels 0/1 detection #17 11 h ffffb8 h icr03 0000b3 h *1 dtp/ext. interrupt channels 2/3 detection #18 12 h ffffb4 h dtp/ext. interrupt channels 4/5 detection #19 13 h ffffb0 h icr04 0000b4 h *1 wake-up interrupt detection #20 14 h ffffac h upi0/1/2/3 obe #21 15 h ffffa8 h icr05 0000b5 h *2 16-bit ppg timer 1 #22 16 h ffffa4 h ps/2 interface 0/1 #23 17 h ffffa0 h icr06 0000b6 h *1 ps/2 interface 2 #24 18 h ffff9c h watch timer #25 19 h ffff98 h icr07 0000b7 h *1 i 2 c transfer complete / bus error #26 1a h ffff94 h 16-bit ppg timer 2/3 #27 1b h ffff90 h icr08 0000b8 h *1 voltage comparator 1 #28 1c h ffff8c h mi 2 c transfer complete / bus error #29 1d h ffff88 h icr09 0000b9 h *1 voltage comparator 2 #30 1e h ffff84 h i 2 c timeout / standby wake-up #31 1f h ffff80 h icr10 0000ba h *1 16-bit reload timer 1/2 underflow #32 20 h ffff7c h mi 2 c timeout / standby wake-up #33 21 h ffff78 h icr11 0000bb h *1 16-bit reload timer 3/4 underflow #34 22 h ffff74 h uart1 receive #35 23 h ffff70 h icr12 0000bc h *1 uart1 send #36 24 h ffff6c h uart2 receive #37 25 h ffff68 h icr13 0000bd h *1 uart2 send #38 26 h ffff64 h uart3 receive #39 27 h ffff60 h icr14 0000be h *1 uart3 send #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h *1 delayed interrupt generator module #42 2a h ffff54 h
mb90370/375 series 38 : can be used and interrupt request flag is cleared by ei 2 os interrupt clear signal. : cannot be used. : can be used and support the ei 2 os stop request. : can be used. *1 : for peripheral functions that share the icr register, the interrupt level will be the same. if the extended intelligent i/o service is to be used with a peripheral function that shares the icr register with another peripheral function, the service can be started by either of the function. and if ei 2 os clear is supported, both interrupt request flags for the two interrupt causes are cleared by ei 2 os interrupt clear signal. it is recommended to mask either of the interrupt request during the use of ei 2 os. ei 2 os service cannot be started multiple times simultaneously. interrupt other than the operating interrupt is masked during ei 2 os operation. it is recommended to mask either of the interrupt requests during the use of ei 2 os. *2 : this priority is applied when interrupts of the same level occur simultaneously.
mb90370/375 series 39 n n n n peripheral resources 1. low-power consumption control circuit the mb90370/375 series has the following cpu operating mode selected by the configuration of an operating clock and clock operation control. ? clock mode ? pll clock mode in this mode, a pll clock that is a multiple of the oscillation clock (hclk) is used to operate the cpu and peripheral functions. ? main clock mode in this mode, the main clock, with the oscillation clock (hclk) frequency divided by 2 is used to operate the cpu and peripheral functions. in the main clock mode, the pll multiplier circuit is inactive. ? sub-clock mode in this mode, the sub-clock, with the sub-clock (sclk) frequency divided by 4 is used to operate the cpu and peripheral functions. in the sub-clock mode, the main clock and pll multiplier circuit are inactive. ? cpu intermittent operating mode in this mode, the cpu is operated intermittently while high-speed clock pluses are supplied to peripheral func- tions, thereby reducing power consumption. in this mode, intermittent clock pulses are supplied only to the cpu while it is accessing a register, internal memory, or peripheral function. ? standby mode in this mode, the low-power consumption control circuit stops supplying the clock to the cpu (sleep mode) or the cpu and peripheral functions (timebase timer mode) or stops the oscillation clock itself (stop mode) , thereby reducing power consumption. ? pll sleep mode the pll sleep mode is activated to stop the cpu operating clock in the pll clock mode. components excluding the cpu operate on the pll clock. ? main sleep mode the main sleep mode is activated to stop the cpu operating clock in the main clock mode. components excluding the cpu operate on the main clock. ? sub-sleep mode the sub-sleep mode is activated to stop the cpu operating clock in the sub-clock mode. components excluding the cpu operate on the divided-by-four sub-clock. ? timebase timer mode the timebase timer mode causes the operation of functions, excluding the oscillation clock, timebase timer, and watch timer, to stop. all functions other than the timebase timer and watch timer are inactivated. ? watch mode and main watch mode the watch mode and main watch mode operates the watch timer only. the sub-clock operates but the main clock and pll multiplier circuit stop. ? stop mode the stop mode causes the oscillation to stop. all functions are inactivated. note : because the stop mode turns the oscillation clock off, data can be retained by the lowest power consumption.
mb90370/375 series 40 (1) register configuration (2) block diagram clock selection register lower power consumption mode control register bit number address : 0000a1 h ckscr read/write initial value bit number address : 0000a0 h lpmcr read/write initial value r 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 0 r/w 0 15 14 13 12 11 10 9 8 mcm r 1 scm ws1 ws0 scs mcs cs1 cs0 w 0 r/w 0 w 1 w 1 r/w 0 r/w 0 r/w 0 76543210 slp w 0 stp spl rst tmd cg1 cg0 reserved x0 2 x1 rst stp rst slp cg1 cg0 spl tmd scm ws0 mcm mcs cs1 cs0 ws1 scs 2 2 low power consumption mode control register (lpmcr) pin pin pin divide- by-2 divide- by-16 divide- by-8 divide- by-128 divide- by-4 divide- by-4 pll multiplier circuit timebase timer stop signal interrupt clearing cpu clock pulse pin hi-z control clock selector clock selection register (ckscr) stop and sleep signals machine clock main clock oscillation stabilization wait time selector oscillation stabiliza- tion wait clearing cpu clock control circuit pin high- impedance control circuit internal reset generation circuit internal reset peripheral clock control circuit cpu intermittent operation selector intermittent cycle selection standby control circuit peripheral clock clock genera- tion part resv x0a pin x1a pin system clock generation circuit divide- by-4 subclock generation circuit subclock
mb90370/375 series 41 2. i/o ports (1) outline of i/o ports each i/o port outputs data from the cpu to the i/o pins or inputs signals from the i/o pins to the cpu as directed by the port data register (pdr) . each cmos i/o port can also designate the direction of a data flow (input or output) at the i/o pins in bit units using the port data direction register (ddr) . or n-channel open-drain port can designate the direction of a data flow (input or output) at the i/o pins in bit units using the port data register (pdr) . the function of each port and the resources using it are described below : ? port 0 : general-purpose i/o port/resource (key-on wake-up interrupt) ? port 1 : general-purpose i/o port ? port 2 : general-purpose i/o port ? port 3 : general-purpose i/o port/resource (a/d converter external trigger) ? port 4 : general-purpose i/o port/resource (ps/2 interface / serial irq controller) ? port 5 : general-purpose i/o port/resource (lpc interface) ? port 6 : general-purpose i/o port/resource (dtp / uart1) ? port 7 : general-purpose i/o port/resource (uart1 / uart2 / uart3 / ppg1) ? port 8 : general-purpose i/o port/resource (multi-address i 2 c) ? port 9 : general-purpose i/o port/resource (i 2 c / multi-address i 2 c) ? port a : general-purpose i/o port/resource (comparator) ? port b : general-purpose i/o port/resource (comparator) ? port c : general-purpose i/o port/resource (comparator / a/d converter) ? port d : general-purpose i/o port/resource (a/d converter / d/a converter / ppg2 / ppg3) ? port e : general-purpose i/o port/resource (reload timer1 to 4 / lcd controller*) ? port f : general-purpose i/o port/resource (lcd controller*) * : lcd controller doesnt exist in mb90f377, and so port e and f of mb90f377 are not used for this purpose. (2) register configuration (continued) register read/write address initial value port 0 data register (pdr0) r/w 000000 h xxxxxxxx b port 1 data register (pdr1) r/w 000001 h xxxxxxxx b port 2 data register (pdr2) r/w 000002 h xxxxxxxx b port 3 data register (pdr3) r/w 000003 h xxxxxxxx b port 4 data register (pdr4) r/w 000004 h x1111111 b port 5 data register (pdr5) r/w 000005 h xxxxxxxx b port 6 data register (pdr6) r/w 000006 h xxxxxxxx b port 7 data register (pdr7) r/w 000007 h xxxxxxxx b port 8 data register (pdr8) r/w 000008 h -----111 b port 9 data register (pdr9) r/w 000009 h --111111 b port a data register (pdra) r/w 00000a h -xxxxxxx b port b data register (pdrb) r/w 00000b h xxxxxxxx b port c data register (pdrc) r/w 00000c h xxxxxxxx b port d data register (pdrd) r/w 00000d h xxxxxxxx b port e data register (pdre) r/w 00000e h xxxxxxxx b
mb90370/375 series 42 (continued) register read/write address initial value port f data register (pdrf) r/w 00000f h xxxxxxxx b port 0 data direction register (ddr0) r/w 000010 h 00000000 b port 1 data direction register (ddr1) r/w 000011 h 00000000 b port 2 data direction register (ddr2) r/w 000012 h 00000000 b port 3 data direction register (ddr3) r/w 000013 h 00000000 b port 4 data direction register (ddr4) r/w 000014 h 0------- b port 5 data direction register (ddr5) r/w 000015 h 00000000 b port 6 data direction register (ddr6) r/w 000016 h 00000000 b port 7 data direction register (ddr7) r/w 000017 h 00000000 b port a data direction register (ddra) r/w 00001a h -0000000 b port b data direction register (ddrb) r/w 00001b h 00000000 b port c data direction register (ddrc) r/w 00001c h 00000000 b port d data direction register (ddrd) r/w 00001d h 00000000 b port e data direction register (ddre) r/w 00001e h 00000000 b port f data direction register (ddrf) r/w 00001f h 00000000 b analog data input enable register (ader1) r/w 00002a h 11111111 b analog data input enable register (ader2) r/w 00002b h ----1111 b comparator input enable register (cier) r/w 0000e0 h ---11111 b lcd control register 1 (lcrh) r/w 0000ef h 00000000 b port 0 pull-up resistor setting register (rdr0) r/w 00008c h 00000000 b port 1 pull-up resistor setting register (rdr1) r/w 00008d h 00000000 b port 2 pull-up resistor setting register (rdr2) r/w 00008e h 00000000 b port 3 pull-up resistor setting register (rdr3) r/w 00008f h 00000000 b port 3 data latch register (pdl3) r/w 0000ea h 00000000 b r/w : read/write enabled x : undefined - : not used
mb90370/375 series 43 (3) block diagram of i/o ports ? block diagram of port 0 pins ? block diagram of port 1 pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) rdr pull-up resistor about 50 k w resource input internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) rdr pull-up resistor about 50 k w
mb90370/375 series 44 ? block diagram of port 2 pins ? block diagram of port 3 pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) rdr pull-up resistor about 50 k w internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) rdr pull-up resistor about 50 k w r port data latch register (pdl) input latch resource input
mb90370/375 series 45 ? block diagram of port 47 pin ? block diagram of port 46 pin internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) resource output resource output enable resource input port data register (pdr) pdr read pdr write output latch pin standby control (spl = 1) resource output resource output enable internal data bus resource input read-modify-write instruction
mb90370/375 series 46 ? block diagram of port 45 to 40 pins ? block diagram of port 5 pins port data register (pdr) pdr read pdr write output latch pin standby control (spl = 1) resource output resource output enable internal data bus resource input read-modify-write instruction internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) resource output resource output enable resource input
mb90370/375 series 47 ? block diagram of port 6 pins ? block diagram of port 7 pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) resource output resource output enable resource input internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) resource output resource output enable resource input
mb90370/375 series 48 ? block diagram of port 8 pins ? block diagram of port 9 pins pdr read pdr write output latch pin standby control (spl = 1) resource output resource output enable internal data bus resource input read-modify-write instruction port data register (pdr) port data register (pdr) pdr read pdr write output latch pin standby control (spl = 1) resource output resource output enable internal data bus resource input read-modify-write instruction
mb90370/375 series 49 ? block diagram of port a pins ? block diagram of port b pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) resource output resource output enable internal data bus pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) port data register (pdr) comparator comparator input enable operation cier
mb90370/375 series 50 ? block diagram of port c7 to c3 pins ? block diagram of port c2 to c0 pins internal data bus ader pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) port data register (pdr) to a/d converter analog input a/d converter channel selection bit internal data bus ader pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) port data register (pdr) cier comparator operation comparator enable bit (cocrh) a/d converter channel selection bit to a/d converter analog input
mb90370/375 series 51 ? block diagram of port d7 and d6 pins ? block diagram of port d5 and d4 pins internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) resource output resource output enable internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) d/a output enable analog output
mb90370/375 series 52 ? block diagram of port d3 to d0 pins ? block diagram of port e pins (not for mb90f377) internal data bus ader pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) port data register (pdr) a/d input internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) resource output resource output enable resource input lcd output lcd output enable
mb90370/375 series 53 ? block diagram of port f7 to f5 pins (not for mb90f377) ? block diagram of port f4 to f0 pins (not for mb90f377) internal data bus vs pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) port data register (pdr) lcd input (v1 to v3) lcrh internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) lcd output enable lcd output
mb90370/375 series 54 3. timebase timer the timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with the internal count clock (one-half of the source oscillation) . features of timebase timer : ? interrupt generated when counter overflow ?ei 2 os supported ? interval timer function : an interrupt generated at four different time intervals ? clock supply function : four different clocks can be selected as watchdog timers count clock. supply clock for oscillation stabilization (1) register configuration (2) block diagram of timebase timer timebase timer control register bit number address : 0000a9 h tbtc read/write initial value ? ? ? ? r/w 0 r/w 0 r/w 1 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? r/w 1 reserved ? tbie tbof tbr tbc1 tbc0 ? : unused of : overflow hclk : oscillation clock *1 : switching of the machine clock from the oscillation clock to the pll clock *2 : switching from main clock to sub-clock tbie resv ? ? tbof tbr tbc1 tbc0 2 1 2 2 2 3 2 8 2 7 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 of of of of to watchdog timer to the oscillation stabilization wait time selector in the clock control section tbof set timebase timer interrupt register (tbtc) timebase timer interrupt signal #12 (0c h ) power-on reset stop mode start ckscr : mcs = 1 ? 0 (*1) scs = 1 ? 0 (*2) counter clear circuit interval timer selector timebase timer counter divide-by -two hclk
mb90370/375 series 55 4. watchdog timer the watchdog timer is a 2-bit counter that uses the timebase timers supply clock as the count clock. after activation, if the watchdog timer is not cleared within a given period, the cpu will be reset. ? features of watchdog timer : reset cpu at four different time intervals status bits to indicate the reset causes (1) register configuration of watchdog timer (2) block diagram of watchdog timer watchdog timer control register bit number address : 0000a8 h wdtc read/write initial value ? ? r x r x r x w 1 w 1 w 1 76543210 ? r x ponr wrst erst srst wte wt1 wt0 watchdog timer control register (wdtc) watchdog timer start of watch mode start of sleep mode start of stop mode reset generation counter clear control circuit count clock selector activation with clr 2-bit counter overflow watchdog reset generator to the internal reset generator clk clr (timebase timer counter) one-half of hclk sub-clock divide by 4 watch timer counter 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 1 2 2 2 10 2 11 2 12 2 13 2 14 2 15 ? ponr wrst erst srst wte wt1 wt0 wdcs (from watch timer control register, wtc) 2 4 4 hclk : oscillation clock
mb90370/375 series 56 5. watch timer the watch timer is a 15-bit timer that uses sub-clocks and can generate an interval interrupt. it can also be used as the watchdog timer clock source and sub-clock oscillation wait time. features of the watch timer : ? provides the watchdog timer clock source ? sub-clock oscillation stabilization wait timer function ? interval timer function that generates interrupts in a given cycle (1) register configuration of watch timer (2) block diagram of watch timer watch timer control register bit number address : 0000aa h wtc read/write initial value r 0 r/w 0 r/w 0 w 1 r/w 0 r/w 0 r/w 0 76543210 sce r/w 1 wdcs wtie wtof wtr wtc2 wtc1 wtc0 watch timer control register (wtc) 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 10 2 13 2 14 2 15 watch counter interval selector clear interrupt generator watch timer interrupt the subclock divided by 4 to the watchdog timer sce wdcs wtie wtof wtr wtc2 wtc1 wtc0
mb90370/375 series 57 6. 16-bit ppg timer ( 3) the 16-bit ppg (programmable pulse generator) timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty setting register, 16-bit control register and a ppg output pin. features of 16-bit ppg timer : ? 8 types of counter operation clock ( f , f /2, f /4, f /8, f /16, f /32, f /64, f /128) can be selected ( f is the machine clock) ? an interrupt is generated when there is a trigger or a counter borrow or when ppg rising (normal polarity) / ppg falling (inverted polarity) . ? ppg output operation the 16-bit ppg timer can output pulse waveforms with variable period and duty ratio. also, it can be used as d/a converter in conjunction with an external circuit. (1) register configuration of ppg timer (continued) ppg down counter register (upper) ppg down counter register (lower) ppg period setting buffer register (upper) ppg period setting buffer register (lower) address : ch1 ch2 ch3 000039 h 000041 h 000049 h bit number pdcrh1 to pdcrh3 read/write initial value address : ch1 ch2 ch3 000038 h 000040 h 000048 h bit number pdcrl1 to pdcrl3 read/write initial value address : ch1 ch2 ch3 00003b h 000043 h 00004b h bit number pcsrh1 to pcsrh3 read/write initial value address : ch1 ch2 ch3 00003a h 000042 h 00004a h bit number pcsrl1 to pcsrl3 read/write initial value 15 14 13 12 11 10 9 8 r 1 r 1 r 1 r 1 r 1 r 1 r 1 dc14 r 1 dc15 dc13 dc12 dc11 dc10 dc09 dc08 76543210 r 1 r 1 r 1 r 1 r 1 r 1 r 1 dc06 r 1 dc07 dc05 dc04 dc03 dc02 dc01 dc00 15 14 13 12 11 10 9 8 w x w x w x w x w x w x w x cs14 w x cs15 cs13 cs12 cs11 cs10 cs09 cs08 76543210 w x w x w x w x w x w x w x cs06 w x cs07 cs05 cs04 cs03 cs02 cs01 cs00
mb90370/375 series 58 (continued) ppg duty setting buffer register (upper) ppg duty setting buffer register (lower) ppg control status register (upper) ppg control status register (lower) address : ch1 ch2 ch3 00003d h 000045 h 00004d h bit number pduth1 to pduth3 read/write initial value address : ch1 ch2 ch3 00003c h 000044 h 00004c h bit number pdutl1 to pdutl3 read/write initial value address : ch1 ch2 ch3 00003f h 000047 h 00004f h bit number pcnth1 to pcnth3 read/write initial value address : ch1 ch2 ch3 00003e h 000046 h 00004e h bit number pcntl1 to pcntl3 read/write initial value 15 14 13 12 11 10 9 8 w x w x w x w x w x w x w x du14 w x du15 du13 du12 du11 du10 du09 du08 76543210 w x w x w x w x w x w x w x du06 w x du07 du05 du04 du03 du02 du01 du00 15 14 13 12 11 10 9 8 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 stgr r/w 0 cnte mdse rtrg cks2 cks1 cks0 pgms 76543210 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 ? ? ? ? iren irqf irs1 irs0 poen osel note : registers pdcr1 to pdcr3, pcsr1 to pcsr3 and pdut1 to pdut3 are word access only.
mb90370/375 series 59 (2) block diagram of ppg timer f 2 mc-16lx bus prescaler period setting buffer register 1/2/3 period setting register 1/2/3 duty setting register 1/2/3 duty setting buffer register 1/2/3 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 cks2 cks1 cks0 clk stop start borrow load 16-bit down counter down counter register 1/2/3 machine clock f comparator s r q mdse pgms osel poen irs1 irs0 irqf stgr cnte rtrg iren pin p77/ppg1 or pd6/ppg2 or pd7/ppg3 interrupt selection interrupt #22 (for ppg1) or #27 (for ppg2/3) gate input
mb90370/375 series 60 7. 16-bit reload timer ( 4) the 16-bit reload timer provides two operating modes, internal clock mode and event count mode. in each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot mode) . output pins to1 to to4 are able to output different waveform according to the counter operating mode. to1 to to4 toggles when counter underflow if counter is operated as reload mode. to1 to to4 output specified level (h or l) when counter is counting if the counter is in one-shot mode. features of the 16-bit reload timer : ? interrupt generated when timer underflow ?ei 2 os supported ? internal clock operating mode : three internal count clocks can be selected. counter can be activated by software or external trigger (signal at tin1 to tin4 pin) . counter can be reloaded or stopped when underflow after activated. ? event count operating mode : counter counts down by one when specified edge at tin1 to tin4 pin. counter can be reloaded or stopped when underflow. (1) register configuration of reload timer timer control status register (upper) timer control status register (lower) 16-bit timer register / 16-bit reload register (upper) 16-bit timer register / 16-bit reload register (lower) address : ch1 ch2 ch3 ch4 000071 h 000075 h 000079 h 00007d h bit number tmcsrh1 to tmcsrh4 read/write initial value address : ch1 ch2 ch3 ch4 000070 h 000074 h 000078 h 00007c h bit number tmcsrl1 to tmcsrl4 read/write initial value address : ch1 ch2 ch3 ch4 000073 h 000077 h 00007b h 00007f h bit number tmr1 to tmr4/ tmrd1 to tmrd4 read/write initial value address : ch1 ch2 ch3 ch4 000072 h 000076 h 00007a h 00007e h bit number tmr1 to tmr4/ tmrd1 to tmrd4 read/write initial value ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ??? csl1 csl0 mod2 mod1 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 oute r/w 0 mod0 outl reld inte uf cnte trg r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 d14 r/w x d15 d13 d12 d11 d10 d09 d08 r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 d06 r/w x d07 d05 d04 d03 d02 d01 d00
mb90370/375 series 61 (2) block diagram of reload timer clk en clk 3 3 2 ???? csl1 csl0 mod2 mod1 mod0 oute outl reld uf inte cnte trg f 2 mc-16lx bus 16-bit reload register reload signal reload control circuit 16-bit timer register count clock generation circuit machine clock prescaler clear gate input valid clock judgment circuit wait signal internal clock pin input control circuit external clock clock selector select signal invert output control circuit output signal generation circuit to uart1* 1 pin function selection operation control circuit timer control status register tmcsr1* 1 interrupt request signal #32 (20 h )* 1, * 2 <#34 (22 h )> tmrd1* 1 pe1/to1/seg1 pe3/to2/seg3 pe5/to3/seg5 pe7/to4/seg7 pe0/tin1/seg0 pe2/tin2/seg2 pe4/tin3/seg4 pe6/tin4/seg6 tmr1* 1 *1 : this register includes channel 1, 2, 3 and 4. the register enclosed in < and > indicates the channel 2, 3 and 4 register. *2 : interrupt numbers : channel 1 and 2 share one interrupt number, channel 3 and 4 share another.
mb90370/375 series 62 8. i 2 c the i 2 c (inter ic bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line (sda) and a serial clock line (scl) . among the devices connected with these two wires, information is transmitted to one another. by recognizing the unique address of each device, it can operate as a transmitting or receiving device in accordance with the function of each device. among these devices, the master/slave relation is estab- lished. the i 2 c interface can connect two or more devices to the bus provided the upper limit of the bus capacitance does not exceed 400 pf. it is a full-fledged multi-master bus equipped with collision detection and communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data transfer simultaneously. the communication adjustment procedure permits only one master to control the bus when two or more masters attempt to control the bus so that messages are not lost or the contents of messages are not changed. multi- master means that multiple masters attempt to control the bus simultaneously without losing messages. this i 2 c interface includes mcu standby mode wake-up function, and a crc-8 calculator that performs automatic packet error code (pec) generation and verification. (1) register configuration of i 2 c (continued) i 2 c bus control register (lower) i 2 c bus control register (upper) i 2 c bus status register (lower) i 2 c bus status register (upper) i 2 c data register bit number address : 000080 h ibcrl read/write initial value bit number address : 000081 h ibcrh read/write initial value bit number address : 000082 h ibsrl read/write initial value bit number address : 000083 h ibsrh read/write initial value bit number address : 000084 h idar read/write initial value ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ??? res pece lbt wue r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 beie r/w 0 ber scc mss ack gcaa inte int r 0 r 0 r 0 r 0 r 0 r 0 r 0 76543210 rsc r 0 bb al lrb trx aas gca fbt ? ? r 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? pmatch wuf tdr tcr mtr str r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 d6 r/w x d7 d5 d4 d3 d2 d1 d0
mb90370/375 series 63 (continued) i 2 c address register i 2 c clock control register i 2 c timeout control register i 2 c timeout clock register i 2 c timeout data register i 2 c slave timeout register i 2 c master timeout register bit number address : 000085 h iadr read/write initial value bit number address : 000086 h iccr read/write initial value bit number address : 000087 h itcr read/write initial value bit number address : 000088 h itoc read/write initial value bit number address : 000089 h itod read/write initial value bit number address : 00008a h isto read/write initial value bit number address : 00008b h imto read/write initial value r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 a6 ? ? ? a5 a4 a3 a2 a1 a0 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? r/w 0 dmbp en cs4 cs3 cs2 cs1 cs0 r/w 0 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 aac ? ? ?? toe ext ts2 ts1 ts0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 c6 r/w 0 c7 c5 c4 c3 c2 c1 c0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 d6 r/w 0 d7 d5 d4 d3 d2 d1 d0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 s6 r/w 0 s6 s5 s4 s3 s2 s1 s0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 m6 r/w 0 m7 m5 m4 m3 m2 m1 m0
mb90370/375 series 64 (2) block diagram of i 2 c f 2 mc16lx internal bus scc beie mss ack gcaa inte int ber al rsc lrb trx fbt bb ibsrl start/stop condition generator clock selector 1 clock selector 2 clock frequency divider 1 clock frequency divider 2 shift clock generator error sync start master enables ack enables gc-ack bus busy repeat start last bit transmission/ reception arbitration lost detector sda line scl line first byte i 2 c enable start/stop condition detector iccr en cs2 cs1 cs0 ibcrl ibcrh interrupt #26 end 8 5 peripheral clock shift clock edge dmbp cs4 cs3 678 16 4 aas gca slave idar register iadr register slave address comparator ibsrl general call timeout detector itcr tdr itod itoc isto imto interrupt #31 crc-8 calculator lbt wue wuf ibcrl tcr mtr str ibsrh ibsrh 32 64 128 256 512
mb90370/375 series 65 9. mi 2 c the multi-address i 2 c (inter ic bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line (sda) and a serial clock line (scl) . among the devices connected with these two wires, information is transmitted to one another. by recognizing the unique address of each device, it can operate as a transmitting or receiving device in accordance with the function of each device. among these devices, the master/slave relation is established. the multi-address i 2 c interface can connect two or more devices to the bus provided the upper limit of the bus capacitance does not exceed 400 pf. it is a full-fledged multi-master bus equipped with collision detection and communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data transfer simultaneously. this macro provides 6 addresses to implement the multi-address function. the communication adjustment procedure permits only one master to control the bus when two or more masters attempt to control the bus so that messages are not lost or the contents of messages are not changed. multi- master means that multiple masters attempt to control the bus simultaneously without losing messages. this multi-address i 2 c interface includes mcu standby mode wake-up function, and a crc-8 calculator that performs automatic packet error code (pec) generation and verification. (1) register configuration of mi 2 c (continued) multi-address i 2 c bus control register (lower) multi-address i 2 c bus control register (upper) multi-address i 2 c bus status register (lower) multi-address i 2 c bus status register (upper) multi-address i 2 c data register bit number address : 0000c0 h mbcrl read/write initial value bit number address : 0000c1 h mbcrh read/write initial value bit number address : 0000c2 h mbsrl read/write initial value bit number address : 0000c3 h mbsrh read/write initial value bit number address : 0000c4 h mdar read/write initial value ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ??? res pece lbt wue r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 beie r/w 0 ber scc mss ack gcaa inte int r 0 r 0 r 0 r 0 r 0 r 0 r 0 76543210 rsc r 0 bb al lrb trx aas gca fbt ? ? r 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? pmatch wuf tdr tcr mtr str r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 d6 r/w x d7 d5 d4 d3 d2 d1 d0
mb90370/375 series 66 (continued) multi-address i 2 c alert register multi-address i 2 c address register 1/3/5 multi-address i 2 c address register 2/4/6 multi-address i 2 c clock control register multi-address i 2 c timeout control register multi-address i 2 c timeout clock register multi-address i 2 c timeout data register bit number address : 0000c5 h malr read/write initial value address ch1 : address ch3 : address ch5 : 0000c6 h 0000c8 h 0000ca h bit number madr1/3/5 read/write initial value address ch2 : address ch4 : address ch6 : 0000c7 h 0000c9 h 0000cb h bit number madr2/4/6 read/write initial value bit number address :0000cc h mccr read/write initial value bit number address :0000cd h mtcr read/write initial value bit number address : 0000ce h mtoc read/write initial value bit number address : 0000cf h mtod read/write initial value ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ??? arae aro arf aen 76543210 r/w x r/w x r/w x r/w x r/w x r/w x r/w x a6 ? ? ? a5 a4 a3 a2 a1 a0 15 14 13 12 11 10 9 8 r/w x r/w x r/w x r/w x r/w x r/w x r/w x a6 ? ? ? a5 a4 a3 a2 a1 a0 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? r/w 0 dmbp en cs4 cs3 cs2 cs1 cs0 r/w 0 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 aac ? ? ?? toe ext ts2 ts1 ts0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 c6 r/w 0 c7 c5 c4 c3 c2 c1 c0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 d6 r/w 0 d7 d5 d4 d3 d2 d1 d0
mb90370/375 series 67 (continued) multi-address i 2 c slave timeout register multi-address i 2 c master timeout register bit number address : 0000d0 h msto read/write initial value bit number address : 0000d1 h mmto read/write initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 s6 r/w 0 s6 s5 s4 s3 s2 s1 s0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 m6 r/w 0 m7 m5 m4 m3 m2 m1 m0
mb90370/375 series 68 (2) block diagram of mi 2 c f 2 mc16lx internal bus scc beie mss ack gcaa inte int ber al rsc lrb trx fbt bb mbsrl start/stop condition generator clock selector 1 clock selector 2 clock frequency divider 1 clock frequency divider 2 shift clock generator error sync start master enables ack enables gc-ack bus busy repeat start last bit transmission/ reception arbitration lost detector sda line scl line first byte multi-address i 2 c enable start/stop condition detector mccr en cs2 cs1 cs0 mbcrl mbcrh interrupt #29 end 8 5 peripheral clock shift clock edge dmbp cs4 cs3 678 16 4 aas gca slave mdar register madr1~6 registers slave address comparator mbsrl general call timeout detector mtcr tdr tcr str mtr mtod aro arf aen mmto mtoc msto arae malr alert line crc-8 calculator lbt interrupt #33 wue wuf mbcrl mbsrh mbsrh 32 64 128 256 512
mb90370/375 series 69 10. bridge circuit the bridge circuit can switch the i/o path of each port to i 2 c or multi-address i 2 c. (1) register configuration of bridge circuit (2) block diagram of bridge circuit bridge circuit selection register bit number address : 00002c h brsr read/write initial value ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ? bm4 bi4 bm3 bi3 bm2 bi2 i 2 c multi-address i 2 c p81/sda1 p80/scl1 p91/sda2 p90/scl2 p93/sda3 p92/scl3 p95/sda4 p94/scl4 brsr i 2 c i/o bi3 bi2 bi4 bm3 bm2 bm4
mb90370/375 series 70 11. comparator this comparator circuit monitors voltage of up to three batteries and automatically controls electric discharge. either parallel discharge or sequential discharge can be selected. ? parallel discharge control in parallel discharge control, all batteries are allowed to discharge when power is not being supplied from the ac adapter. ? if power is being supplied from the ac adapter, the permission/prohibition of discharge for batteries is controlled by software. ? sequential discharge control in sequential discharge control, the comparator controls discharge in a specified order, while monitoring intermittent interruption of power, voltage level, and mount/dismount of batteries, when power is not being supplied from the ac adapter. ? if power is being supplied from the ac adapter, the permission/prohibition of discharge for batteries is controlled by software. ? up to three batteries can be controlled, and the order of discharge can be selected. ? the affect of intermittent interruption of power is automatically filtered. ? mount/dismount of batteries is automatically detected and discharge is controlled. ? battery voltage is monitored, and if battery voltage is below the specified voltage, a change over to the next battery is automatically done.
mb90370/375 series 71 (1) register configuration of comparator (continued) comparator control register (lower) comparator control register (upper) comparator status register 1 (lower) comparator status register 1 (upper) comparator interrupt control register (lower) bit number address : 0000d8 h cocrl read/write initial value bit number address : 0000d9 h cocrh read/write initial value bit number address : 0000da h cosrl1 read/write initial value bit number address : 0000db h cosrh1 read/write initial value bit number address :0000dc h cicrl read/write initial value ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ? bof3 bof2 bof1 spm2 spm1 spm0 r/w 0 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 15 14 13 12 11 10 9 8 spl2 r/w 0 spl3 spl1 b3 b2 b1 dc2 dc1 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 cor7 r/w 0 cor8 cor6 cor5 cor4 cor3 cor2 cor1 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? swr3 swr2 swr1 var3 var2 var1 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 cen7 r/w 0 cen8 cen6 cen5 cen4 cen3 cen2 cen1
mb90370/375 series 72 (continued) comparator interrupt control register (upper) comparator status register 2 (lower) comparator status register 2 (upper) comparator input enable register bit number address :0000dd h cicrh read/write initial value bit number address : 0000de h cosrl2 read/write initial value bit number address : 0000df h cosrh2 read/write initial value bit number address : 0000e0 h cier read/write initial value ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? sen3 sen2 sen1 ven3 ven2 ven1 r x r x r x r x r x r x r x 76543210 cos7 r x cos8 cos6 cos5 cos4 cos3 cos2 cos1 ? ? r x r x r x r x r x r x 15 14 13 12 11 10 9 8 ? ? ? ? sws3 sws2 sws1 val3 val2 val1 ? ? ? ? r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 76543210 ? ? ? ?? bie3 bie2 bie1 die2 die1
mb90370/375 series 73 (2) block diagram of comparator (cosrl2) comparator status register 2 (lower) power-on v cc rst decoder 3 6 battery valid (cosrh1) comparator status register 1 (upper) alarm 3 o32 o31 o23 o21 battery valid alarm battery pb5/vsi2 pb4/vol2 valid alarm pc1/an1/sw2 o13 o12 internal data bus battery selection circuit spm0 (cocrl) comparator control register (lower) spm1 spm2 bof1 bof2 bof3 cvrh1 cvrl cvrh2 pb0/dcin pb7/vsi3 pb6/vol3 pc2/an2/sw3 pb3/vsi1 pc0/an0/sw1 pb2/vol1 vol vsi sw ofb vol vsi sw ofb vol vsi sw ofb var1 ven1 var2 ven2 var3 ven3 cen4 cen5 cen6 cen1 cen2 cen3 cen7 (cicrh) comparator interrupt control register (upper) interrupt request (cicrl) comparator interrupt control register (lower) (cosrh2) comparator status register 2 (upper) 8 rh rl (voltage in out rh rl (voltage in out rh rl (voltage in out rh rl (voltage in out rh rl (voltage in out rh rl (voltage in out val1 val2 val3 pb1/dcin2 rh rl (voltage in out swr1 swr2 swr3 sen1 sen2 sen3 + - + - + - 3 cen8 xoa x1a watch sws1 dc1 dc2 b1 b2 (cocrh) comparator control register (upper) b3 sw sw sw sw sw sw sw sws2 sws3 cor4 cor5 cor6 cor1 cor2 cor3 cor7 cor8 cos4 cos5 cos6 cos1 cos2 cos3 cos7 cos8 (cosrl1) comparator status register 1 (lower) + - comparator 1 comparator 2 comparator 3 comparator 4 pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin pin comparator 2) reset prescaler supervisory circuit 1 supervisory circuit 2 supervisory circuit 3 comparator 5) comparator 6) comparator 7) comparator 8) comparator 3) comparator 4) #30 interrupt request #28 spl1 spl2 spl3 spl spl spl 3 pa5/ofb2 pa6/ofb3 pa2/alr3 pa0/alr1 pin pin pin pin pa3/aco pa4/ofb1 pa1/alr2 pin pin pin
mb90370/375 series 74 12. uart ( 3) the uart (universal asychronous receiver transmitter) is a serial i/o port for asynchronous (start-stop) com- munication or clock-synchronous communication. the uart has the following features : ? full-duplex double buffering ? capable of asynchronous (start-stop bit) and clk-synchronous communications ? support for the multiprocessor mode ? various method of baud rate generation : - external clock input possible - internal clock (a clock supplied from 16-bit reload timer can be used) - embedded dedicated baud rate generator ? error detection functions (parity, framing, overrun) ? nrz (non return to zero) signal format ? interrupt request : - receive interrupt (receive complete, receive error detection) - transmit interrupt (transmission complete) - transmit / receive conforms to extended intelligent i/o service (ei 2 os) operation baud rate asynchronous 76923 / 38461 / 19230 / 9615 / 500k / 250k bps clk synchronous 16m / 8m / 4m / 2m / 1m / 500k bps
mb90370/375 series 75 (1) register configuration of uart serial mode register serial control register uart input data register / output data register uart status register clock division control register mode 2 control register address : ch1 ch2 ch3 000020 h 0000d2 h 0000e4 h bit number smr1/2/3 read/write initial value address : ch1 ch2 ch3 000021 h 0000d3 h 0000e5 h bit number scr1/2/3 read/write initial value address : ch1 ch2 ch3 000022 h 0000d4 h 0000e6 h bit number sidr1/2/3 sodr1/2/3 read/write initial value address : ch1 ch2 ch3 000023 h 0000d5 h 0000e7 h bit number ssr1/2/3 read/write initial value address : ch1 ch2 ch3 000025 h 0000d7 h 0000e9 h bit number cdcr1/2/3 read/write initial value address : ch1 ch2 ch3 000024 h 0000d6 h 0000e8 h bit number m2cr1/2/3 read/write initial value 76543210 r/w 0 r/w 0 r/w 0 r/w 0 ? ? r/w 0 r/w 0 md0 r/w 0 md1 cs2 cs1 cs0 ? scke soe 15 14 13 12 11 10 9 8 r/w 0 r/w 0 r/w 0 r/w 0 w 1 r/w 0 r/w 0 p r/w 0 pen sbl cl a/d rec rxe txe 76543210 r/w x r/w x r/w x r/w x r/w x r/w x r/w x d6 r/w x d7 d5 d4 d3 d2 d1 d0 15 14 13 12 11 10 9 8 r 0 r 0 r 0 r 1 r/w 0 r/w 0 r/w 0 ore r 0 pe fre rdrf tfre bds rie tie 15 14 13 12 11 10 9 8 ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 md ?? div3 div2 div1 div0 ? ? ? 76543210 ? ? ? ? ? ? r/w 1 r/w 0 r/w 0 r/w 0 ? ? ? ??? sckl m2l2 m2l1 m2l0
mb90370/375 series 76 (2) block diagram of uart pe ore fre rdrf tdre bds rie tie sckl m2l2 m2l1 m2l0 sidr1/2/3 reception interrupt #35 (23 h )* <#37 (25 h )*> <#39 (27 h )*> 16-bit reload timer 1/2/3 external clock sodr1/2/3 reception clock transmission clock reception control circuit transmission control circuit start bit detection circuit reception bit counter reception parity counter reception shifter transmission start circuit transmission bit counter transmission parity counter p67/uo1 transmission shifter clock selection circuit reception status judgement circuit md1 md0 cs2 cs1 cs0 scke soe smr1/2/3 registers ssr1/2/3 registers pen p sbl cl a / d rec rxe txe scr1/2/3 registers m2cr1/2/3 registers f 2 mc-16lx bus from communication prescaler baud rate generator ei 2 os reception error signal (to cpu) transmission interrupt #36 (24 h )* <#38 (26 h )*> <#40 (28 h )*> end of reception start of transmission control bus control signal p66/uck1 p70/ui1 * : interrupt number
mb90370/375 series 77 13. lcd controller/driver (not for mb90f377) the lcd (liquid crystal display) controller/driver function displays the contents of a display data memory directly to the lcd panel by segment and common outputs. ? up to nine segment outputs (seg0 to seg8) and four common outputs (com0 to com3) may be used. ? built-in display ram. ? three selectable duty ratios (1/2, 1/3, and 1/4) . however, not all duty ratios are available with all bias settings. ? either the main or sub-clock can be selected as the drive clock. ? lcd can be driven directly. table below shows the duty ratios available with each bias setting. : recommended mode x : do not use (1) register configuration of lcd part number bias 1/2 duty ratio 1/3 duty ratio 1/4 duty ratio mb90370 series 1/2 bias x x 1/3 bias x lcdc control register (upper) lcdc control register (lower) bit number address : 0000ef h lcrh read/write initial value bit number address : 0000ee h lcrl read/write initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 vs r/w 0 ss4 cs1 cs0 ss3 ss2 ss1 ss0 r/w 0 r/w 0 r/w 1 r/w 0 r/w 0 r/w 0 r/w 0 76543210 lcen r/w 0 css vsel bk ms1 ms0 fp1 fp0
mb90370/375 series 78 (2) block diagram of lcd 4 4 9 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 internal bus hclk / 2 8 sub-clock (32 khz) lcdc control register (lcr) prescaler timing controller display ram 9 x 4 bit controller driver lcdc supply voltage (v1 to v3) v/i converter common output driver segment output driver
mb90370/375 series 79 14. a/d converter the a/d (analog to digital) converter converts the analog voltage input to an analog input pin (input voltage) to a digital value. the converter has the following features : ? the minimum conversion time is 6.13 m s (for a machine clock of 16 mhz; includes the sampling time) . ? the minimum sampling time is 3.75 m s (for a machine clock of 16 mhz) . ? the converter uses the rc-type successive approximation conversion method with a sample and hold circuit. ? a resolution of 10 bits or 8 bits can be selected. ? up to twelve channels for analog input pins can be selected by a program. ? various conversion modes : - single conversion mode : selectively convert one channel. - scan conversion mode : continuously convert multiple channels. maximum of 12 selectable channels. - continuous conversion mode : repeatedly convert specified channels. - stop conversion mode : convert one channel then halt until the next activation. (enables synchronization of the conversion start timing.) ? at the end of a/d conversion, an interrupt request can be generated and ei2os can be activated. ? in the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. ? the conversion can be activated by software, 16-bit reload timer 4 (rise edge) and adtg. (1) register configuration of a/d converter (continued) analog input enable register 2 analog input enable register 1 a/d control status register 1 a/d control status register 0 bit number address : 00002b h ader2 read/write initial value bit number address : 00002a h ader1 read/write initial value bit number address : 000031 h adcs1 read/write initial value bit number address : 000030 h adcs0 read/write initial value ? ? ? ? ? ? r/w 1 r/w 1 r/w 1 r/w 1 15 14 13 12 11 10 9 8 ? ? ? ??? ade11 ade10 ade9 ade8 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 r/w 1 76543210 ade6 r/w 1 ade7 ade5 ade4 ade3 ade2 ade1 ade0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 w 0 r/w 0 15 14 13 12 11 10 9 8 int r/w 0 busy inte paus sts1 sts0 strt resv r/w 0 ? ? ? ? ? ? ? ? ? ? ? ? 76543210 md0 r/w 0 md1 ??????
mb90370/375 series 80 (continued) (2) block diagram of a/d converter a/d control register a/d data register (upper) a/d data register (lower) bit number address : 00002d h adc0 read/write initial value bit number address : 00002f h adcr1 read/write initial value bit number address : 00002e h adcr0 read/write initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ans2 r/w 0 ans3 ans1 ans0 ane3 ane2 ane1 ane0 w 0 w 0 w 0 w 0 ? ? r x r x 15 14 13 12 11 10 9 8 st1 r/w 0 s10 st0 ct1 ct0 ? d9 d8 r x r x r x r x r x r x r x 76543210 d6 r x d7 d5 d4 d3 d2 d1 d0 f mp comparator decoder input circuit an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 sample and holding circuit operation clock adcr0/1 adcs0/1 prescalar 16-bit reload timer 4 p37/adtg avcc d/a converter data register a/d control status register 0 a/d control register a/d control status register 1 sequential comparison register avr avss f 2 mc-16lx bus f : machine clock
mb90370/375 series 81 15. d/a converter the d/a (digital to analog) converter is used to generate an analog output from an 8-bit digital input. by setting the enable bit in the d/a control register (dacr) to 1, it will enable the corresponding d/a output channel. hence, setting this bit to 0 will disable that channel. if d/a output is disabled, the analog switch inserted to the output of each d/a converter channel in series is turned off. in the d/a converter, the bit is cleared to 0 and the direct-current path is shut off. the above is also true in the stop mode. the output voltage of the d/a converter ranges from 0 v to 255/256 x av cc . the d/a converter output does not have the internal buffer amplifier. the analog switch ( = 100 w) is inserted to the output in series. to apply load to the output externally, estimate a sufficient stabilization time. table below lists the theoretical values of output voltage of the d/a converter. value written to da07 to da00 and da17 to da10 theoretical value of output voltage 00 h 0/256 av cc ( = 0 v) 01 h 1/256 av cc 02 h 2/256 av cc : : fd h 253/256 av cc fe h 254/256 av cc ff h 255/256 av cc
mb90370/375 series 82 (1) register configuration of d/a converter d/a converter register 1 d/a converter register 0 d/a control register 1 d/a control register 0 bit number address : 00005b h dat1 read/write initial value bit number address : 00005a h dat0 read/write initial value bit number address : 00005d h dacr1 read/write initial value bit number address : 00005c h dacr0 read/write initial value r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 da16 r/w x da17 da15 da14 da13 da12 da11 da10 r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 da06 r/w x da07 da05 da04 da03 da02 da01 da00 ? ? ? ? ? ? ? ? ? ? ? ? r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? ????? dae1 ? ? ? ? ? ? ? ? ? ? ? ? r/w 0 76543210 ? ? ? ?????? dae0
mb90370/375 series 83 (2) block diagram of d/a converter f 2 mc-16lx bus da da da da da da da da da da da da da da da da 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 av cc av cc da17 da07 2r 2r rr da16 da06 2r 2r rr da15 da05 da11 da01 2r 2r rr da10 da00 2r 2r 2r 2r dae1 standby control dae0 standby control da output ch.1 da output ch.0
mb90370/375 series 84 16. lpc interface the lpc (low pin count) interface consists of an lpc bus interface, universal parallel interface (upi 4 channels) , gate address a20 function and lpc data buffer array. by using the lpc bus interface and upi, data can be exchanged with an external host cpu synchronously via an external lpc bus. ?lpc bus interface the lpc bus interface provides direct access of host cpu to upi. it supports i/o read and i/o write cycle only. other cycle types will be ignored. it supports lpc clock running at 33 mhz. ? universal parallel interface, upi 4 channels the upi is used to exchange parallel data to serial data in lpc bus with host cpu. an 8-bit data will be transmitted or received. a buffer function is available for independent input and output. the i/o buffer status can be output externally through lpc bus interface. ? gate address a20 function for upi channel 0 the ga20 (gate address a20) is intended to implement the memory management in a pc architecture. this allows the access to the extended memory needed by the operating system. on-chip logic is provided to speed up the generation of ga20. ? data buffer array the data buffer array is consisted of 32 bytes up data register and 16 bytes down data register to speed up the data transfer between mcu and external host through lpc bus. (1) register configuration of lpc bus interface register lpc control register bit number address : 00006e h lcr read/write initial value ? ? ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 76543210 ? ? ? ???? lrf lrie lpe
mb90370/375 series 85 (2) register configuration of upi registers upi address register (upper) upi address register (lower) upi control register (upper) upi control register (lower) upi status register upi data input register / data output register address : ch1 ch2 ch3 00005f h 000061 h 000063 h bit number upah1 to upah3 read/write initial value address : ch1 ch2 ch3 00005e h 000060 h 000062 h bit number upal1 to upal3 read/write initial value bit number address : 000065 h upch read/write initial value bit number address : 000064 h upcl read/write initial value address : ch0 ch1 ch2 ch3 000067 h 000069 h 00006b h 00006d h bit number ups0 to ups3 read/write initial value address : ch0 ch1 ch2 ch3 000066 h 000068 h 00006a h 00006c h bit number updi0 to updi3/ updo0 to updo3 read/write initial value 15 14 13 12 11 10 9 8 r/w x r/w x r/w x r/w x r/w x r/w x r/w x upa14 r/w x upa15 upa13 upa12 upa11 upa10 upa09 upa08 76543210 r/w x r/w x r/w x r/w x r/w x r/w x r/w x upa06 r/w x upa07 upa05 upa04 upa03 upa02 upa01 upa00 r/w 0 r/w 0 r/w 0 ? ? r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 upe3 ? ? ? ibfe3 obee3 ? upe2 ibfe2 obee2 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 upe1 r/w 0 dbae ibfe1 obee1 ga20e upe0 ibfe0 obee0 15 14 13 12 11 10 9 8 r/w 0 r/w 0 r/w 0 r 0 r/w 0 r 0 r 0 uf3 r/w 0 uf4 uf2 uf1 a2 uf0 ibf obf 76543210 r/w x r/w x r/w x r/w x r/w x r/w x r/w x upd6 r/w x upd7 upd5 upd4 upd3 upd2 upd1 upd0
mb90370/375 series 86 (3) register configuration of lpc data buffer registers (continued) data buffer array address register (upper) data buffer array address register (lower) up data register (upper) up data register (lower) down data register (upper) down data register (lower) bit number address : 003ff1 h dbaah read/write initial value bit number address : 003ff0 h dbaal read/write initial value address : ch0 ch1 chf 003fc1 h 003fc3 h to 003fdf h bit number udrh0 to udrhf read/write initial value address : ch0 ch1 chf 003fc0 h 003fc2 h to 003fde h bit number udrl0 to udrlf read/write initial value address : ch0 ch1 ch7 003fe1 h 003fe3 h to 003fef h bit number dndh0 to dndh7 read/write initial value address : ch0 ch1 ch7 003fe0 h 003fe2 h to 003fee h bit number dndl0 to dndl7 read/write initial value r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 da14 r/w x da15 da13 da12 da11 da10 da09 da08 r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 da06 r/w x da07 da05 da04 da03 da02 da01 da00 15 14 13 12 11 10 9 8 r/w x r/w x r/w x r/w x r/w x r/w x r/w x up14 r/w x up15 up13 up12 up11 up10 up09 up08 76543210 r/w x r/w x r/w x r/w x r/w x r/w x r/w x up06 r/w x up07 up05 up04 up03 up02 up01 up00 15 14 13 12 11 10 9 8 r x r x r x r x r x r x r x dn14 r x dn15 dn13 dn12 dn11 dn10 dn09 dn08 76543210 r x r x r x r x r x r x r x dn06 r x dn07 dn05 dn04 dn03 dn02 dn01 dn00
mb90370/375 series 87 (continued) (4) block diagram of lpc interface index register data port register bit number address : ? ixr read/write initial value bit number address : ? dpr read/write initial value ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ? ix05 ix04 ix03 ix02 ix01 ix00 r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 dp06 r/w x dp07 dp05 dp04 dp03 dp02 dp01 dp00 f 2 mc-16lx internal data bus upi address register, upah1 to upah3, upal1 to upal3 data buffer array address register, dbaa ibfe upe obee uf3 uf4 uf2 a2 uf1 uf0 ibf obf upd6 upd7 upd5 upd3 upd4 upd2 upd1 upd0 upd6 upd7 ga20e dbae upd5 upd3 upd4 upd2 upd1 upd0 upc ups updi updo upc upc upi0 to upi3 for upi0 only en ga20 output generator up data register (32 bytes) down data register (16 bytes) data buffer array ixr dpr index register data port register lpc internal data bus address comparator upe lpc/rw r/w comp match dbae interrupt request #16 interrupt request #15 interrupt request #14 interrupt request #13 interrupt request #21 obf0 to obf3 lcr lrf lrie lpe la3 la2 la1 la0 ld7 ld6 ld5 ld4 ld3 ld2 ld1 ld0 en r/w state machine lframe lreset lclk lad3 to lad0 4 lpc bus interface ga20
mb90370/375 series 88 17. serial irq controller the serial irq controller consists of a 6-channel serial irq control circuit and an lpc clock monitor / control circuit. by using this serial irq controller, host interrupt requests can be transferred serially through a single signal wire (serirq) , synchronized with the lpc clock. 6-channel serial irq control circuit ? the 6-channel serial irq control circuit consists of a serial interrupt control register (sicr) , 4 serial interrupt frame number registers (sifr1 to sifr4) , a protocol state machine and a serial interrupt data latch and output control. ? for channel 0a, 0b and 1 to 3, if sicr : obe bit (obf controlled enable bit) = 0, then serial irq can be controlled by software setting of sicr : irr bit. if sicr : obe bit = 1, then software control is disabled and serial irq is controlled by obf flag (output buffer full flag) from lpc upi0 to upi3. ? for channel 4, serial irq can be controlled by software setting of sicr : irr bit. ? for channel 0a and 0b, additional enable bit (sicr : en0a/0b bit) can be used to latch and keep the obf0 or irr0a/0b bit status. ? the serial interrupt data latch transfers serial irqs serially according to their frame number. the frame number for channel 0a is fixed to irq1, for channel 0b is fixed to irq12, and the frame number for channel 1 to channel 4 are software programmable (irq1 to irq15, and irq21 to irq31) by setting the sifr1 to sifr4. ? by monitoring the serirq and the lpc clock pin, the protocol state machine can detect the start frame condition. then it starts counting the data frame and transfers its serial irqs through serirq. finally it can switch to continuous/quiet mode operation by determine the stop frame condition. ? the serial interrupt output control support both continuous and quiet mode operation. in continuous mode operation, only the host can initiate the serial irqs transfer; in quiet mode operation, both the host and slave (e.g. the serial irq controller) can initiate the serial irqs transfer. lpc clock monitor / / / / control circuit ? the lpc clock monitor / control circuit consists of a clock-run monitor / control circuit. by monitoring the clock- run pin (clkrun ) , the clock monitor / control circuit can determine whether the host has stopped lpc clock in quiet mode operation or not. if lpc clock is stopped and the controller wants to initiate the serial irqs transfer, then it can request the host to restart the lpc clock by controlling the clkrun pin.
mb90370/375 series 89 (1) register configuration of serial irq controller serial interrupt control register (lower) serial interrupt control register (upper) serial interrupt frame number register 1 serial interrupt frame number register 2 serial interrupt frame number register 3 serial interrupt frame number register 4 bit number address : 000032 h sicrl read/write initial value bit number address : 000033 h sicrh read/write initial value bit number address : 000034 h sifr1 read/write initial value bit number address : 000035 h sifr2 read/write initial value bit number address : 000036 h sifr3 read/write initial value bit number address : 000037 h sifr4 read/write initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 en0a r/w 0 en0b irr4 irr3 irr2 irr1 irr0b irr0a r/w 0 r 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 rsen r/w 0 irqen busy obe3 obe2 obe1 obe0b obe0a ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ? lv1 fr14 fr13 fr12 fr11 fr10 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? lv2 fr24 fr23 fr22 fr21 fr20 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ? lv3 fr34 fr33 fr32 fr31 fr30 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? lv4 fr44 fr43 fr42 fr41 fr40
mb90370/375 series 90 (2) block diagram of the serial irq controller obf0 obf1 obf2 obf3 sirq lclk lclk lreset obf0 obf1 obf2 obf3 6-channel serial irq control circuit lclk stop status lclk restart request lpc clock monitor / control circuit serial irq controller from upi0 to upi3 in lpc interface f 2 mc-16lx bus lreset crun serirq lck lreset clkrun pin pin pin pin
mb90370/375 series 91 (3) block diagram of the 6-channel serial irq control circuit f 2 mc-16lx bus serial interrupt control register (upper) serial interrupt control register (lower) serial interrupt frame number register serirq busy register write disable irqen obe0a, obe0b, obe1 to obe3 irr0a, irr0b, irr1 to irr3 irr4 en0a, en0b software control hardware control serial irq control selector for channel 0a, 0b, 1 to 3 latches for channel 0a, 0b serial interrupt data latch and output control serial irqs frame no. for channel 1 to channel 4 serial irq sample cycle frame cycle count initiate serial irq transfer request protocol state machine channel 1 to channel 4 sirq enable obf0 obf1 obf2 obf3 sirqo lck sirqi lck stop status lck restart request lreset
mb90370/375 series 92 (4) block diagram of the lpc clock monitor / control circuit f 2 mc-16lx bus lck restart request lck restart request cruno enable lck stop status clock-run monitor / control rsen irqen cruno lreset cruni lck
mb90370/375 series 93 18. 3-channel ps/2 interface the 3-channel ps/2 interface consists of 3 individual channels of ps/2 interface that can be operated concur- rently. ps/2 interface is a two wires, bidirectional serial bus providing economical way for data exchange between host (keyboard controller) and device (keyboard / mouse, etc) . (1) register configuration of 3-channel ps/2 interface ps/2 interface mode register ps/2 interface data register (ch 1) ps/2 interface data register (ch 0, ch 2) ps/2 interface status register ps/2 interface control register bit number address : 000059 h psmr read/write initial value bit number address : 000057 h psdr1 read/write initial value address : ch1 ch2 000056 h 000058 h bit number psdr0/2 read/write initial value address : ch0 ch1 ch2 000051 h 000053 h 000055 h bit number pssr0/1/2 read/write initial value address : ch0 ch1 ch2 000050 h 000052 h 000054 h bit number pscr0/1/2 read/write initial value ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ??? nfs1 nfs0 div1 div0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 d6 r/w 0 d7 d5 d4 d3 d2 d1 d0 76543210 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 d6 r/w 0 d7 d5 d4 d3 d2 d1 d0 15 14 13 12 11 10 9 8 r 0 r 0 r 0 r 0 r 0 r 0 r/w 0 fed r 0 pe fre/nak raf ts tbc bnr tc 76543210 ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 ? r/w 0 ps2e ? fede ie breq te re
mb90370/375 series 94 (2) block diagram of 3-channel ps/2 interface f 2 mc-16lx bus nfs1 psmr prescaler circuit 1/4 1/8 1/16 1/32 nfs0 div1 div0 ???? 2 f selector pscki0 psdai0 pscki1 psdai1 pscki2 psdai2 noise filter noise filter noise filter noise filter noise filter noise filter pscko0 psdao0 pscko1 psdao1 pscko2 psdao2 interrupt request 0 interrupt request 1 interrupt request 2 sampling clock channel 0 transmission/ reception circuit channel 1 transmission/ reception circuit channel 2 transmission/ reception circuit
mb90370/375 series 95 (3) block diagram of ps/2 interface transmission/reception circuit (1 channel) f 2 mc-16lx bus f 2 mc-16lx bus d3 psdr psdao d2 d1 d0 d7 d6 d5 d4 ts pssr tbc bnr tc pe fed fre/ nak raf ie pscr breq te re ps2e ?? fede sampling clock synchronous circuit psdai synda synck pscki start of reception reception enable transfer break request transfer status flags clear falling edge detection error flags pe & fre reception active reception complete acknowledge result transmission complete pscko transmission enable start of transmission reception control circuit transmission control circuit reception completion detector acknowledge reception generator parity checker parity generator reception start bit detection circuit reception status judgment circuit transmission completion detector transfer complete processing circuit ps/2 interface interrupt #23 (17 h )* ch0/1 #24 (18 h )* ch2 * : interrupt number
mb90370/375 series 96 19. parity generator the parity generator is a simple circuit that generates odd / even parity based on the input data. it consists of a parity generator data register (pgdr) , an odd / even parity generation logic and a parity generator control status register (pgcsr) . an 8-bit data can be loaded into pgdr, then the parity generator will generate odd / even parity based on the input data. either odd or even parity can be generated by setting the pgcsr. for odd parity generation, if the number of 1s in the pgdr is even number, then the parity bit in pgcsr will be set to 1, otherwise the parity bit will be set to 0. for even parity generation, if the number of 1s in the pgdr is even number, then the parity bit in pgcsr will be set to 0, otherwise the parity bit will be set to 1. table shows some examples of odd / even parity generation. (1) register configuration of parity generator input data parity bit (odd parity) parity bit (even parity) 0000 0000 b 0101 0101 b 1000 0000 b 1010 1011 b 1 1 0 0 0 0 1 1 parity generator data register parity generator control status register bit number address : 000018 h pgdr read/write initial value bit number address : 000019 h pgcsr read/write initial value r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 d6 r/w x d7 d5 d4 d3 d2 d1 d0 ? ? ? ? ? ? ? ? ? ? ? ? r/w 0 15 14 13 12 11 10 9 8 ? r x prty ????? psel
mb90370/375 series 97 (2) block diagram of parity generator f 2 mc16lx internal bus parity generator data register parity generation logic parity generator control status register 8 8 result odd / even 2
mb90370/375 series 98 20. bit decoder the bit decoder is a simple one-hot decoder that can be used together with the keyscan inputs. it consists of a bit data register (bdr) , a decoder logic and a bit result register (brr) . a 4-bit encoded data can be loaded into bdr, then the decoder logic will decode the data and store the 16-bit resulted data into brr. a table below shows the decoders logic. (1) register configuration of bit decoder 4-bit encoded data 16-bit resulted data 0 h 1 h 2 h 3 h 4 h 5 h 6 h 7 h 8 h 9 h a h b h c h d h e h f h 0000 0000 0000 0001 b 0000 0000 0000 0010 b 0000 0000 0000 0100 b 0000 0000 0000 1000 b 0000 0000 0001 0000 b 0000 0000 0010 0000 b 0000 0000 0100 0000 b 0000 0000 1000 0000 b 0000 0001 0000 0000 b 0000 0010 0000 0000 b 0000 0100 0000 0000 b 0000 1000 0000 0000 b 0001 0000 0000 0000 b 0010 0000 0000 0000 b 0100 0000 0000 0000 b 1000 0000 0000 0000 b bit data register bit result register (upper) bit result register (lower) bit number address : 0000e1 h bdr read/write initial value bit number address : 0000e3 h brrh read/write initial value bit number address : 0000e2 h brrl read/write initial value ? ? ? ? ? ? r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 ? ? ? ??? d3 d2 d1 d0 r x r x r x r x r x r x r x 15 14 13 12 11 10 9 8 r14 r x r15 r13 r12 r11 r10 r9 r8 r x r x r x r x r x r x r x 76543210 r6 r x r7 r5 r4 r3 r2 r1 r0
mb90370/375 series 99 (2) block diagram of bit decoder f 2 mc16lx internal bus bit data register decoder logic bit result register 4 4 16 16
mb90370/375 series 100 21. wake-up interrupt the wake-up interrupt circuit detects the signals of the l levels input to the external interrupt pins and to generate interrupt request to the cpu. these interrupts can wake up the cpu from standby mode. (1) register configuration of wake-up interrupt (2) block diagram of wake-up interrupt wake-up interrupt pins : 8 pins (p00/ksi0 to p07/ksi7) . wake-up interrupt sources : l level signal input to a wake-up interrupt pin. interrupt control : enables or disables to input wake-up interrupt controlled by wake-up interrupt control register (eicr) . interrupt flag : irq flag bit of wake-up interrupt flag register (eifr) . flag set when there is an irq. interrupt request : interrupt request #20 is generated if any enabled external interrupt pin goes low. wake-up interrupt flag register wake-up interrupt control register bit number address : 0000ad h eifr read/write initial value bit number address : 0000ac h eicr read/write initial value ? ? ? ? ? ? ? ? ? ? ? ? r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? ????? wif r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 en6 r/w 0 en7 en5 en4 en3 en2 en1 en0 p07/ksi7 p00/ksi0 p01/ksi1 p02/ksi2 p03/ksi3 p04/ksi4 p05/ksi5 p06/ksi6 eicr 7 65 4 3210 interrupt request generator eifr
mb90370/375 series 101 22. dtp/external interrupts the dtp (data transfer peripheral) /external interrupt circuit is activated by the signal supplied to a dtp/external interrupt pin. the cpu accepts the signal using the same as procedure used for normal hardware interrupts and generates external interrupts or activates the extended intelligent i/o service (ei 2 os) . features of dtp/external interrupt : ? total 6 external interrupt channels ? two request levels (h and l) are provided for the intelligent i/o service. ? four request levels (rise/fall edge, fall edge, h level and l level) are provided for external interrupt requests . (1) register configuration dtp/interrupt source register dtp/interrupt enable register request level setting register (upper) request level setting register (lower) bit number address : 000027 h eirr read/write initial value bit number address : 000026 h enir read/write initial value bit number address : 000029 h elvrh read/write initial value bit number address : 000028 h elvrl read/write initial value ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? er5 er4 er3 er2 er1 er0 ? ? r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ? en5 en4 en3 en2 en1 en0 ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 15 14 13 12 11 10 9 8 ? ? ? ??? lb5 la5 lb4 la4 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 76543210 la3 r/w 0 lb3 lb2 la2 lb1 la1 lb0 la0
mb90370/375 series 102 (2) block diagram of dtp/external interrupts request level setting register (elvr) p60/int0 pin p61/int1 pin p62/int2 pin p63/int3 pin p64/int4 pin p65/int5 pin lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 selector selector selector selector selector selector er5 er4 er3 er2 er1 er0 en5 en4 en3 en2 en1 en0 interrupt request number #17(11 h ) #18(12 h ) #19(13 h ) internal data bus 22 2 2 2 2 dtp/interrupt cause register (eirr) dtp/interrupt enable register (enir)
mb90370/375 series 103 23. delayed interrupt generation module the delayed interrupt generation module is used to generate a task switching interrupt. interrupt requests to the f 2 mc-16lx cpu can be generated and cleared by software using this module. (1) register configuration (2) block diagram delayed interrupt generator module register bit number address : 00009f h dirr read/write initial value ? ? ? ? ? ? ? ? ? ? ? ? r/w 0 15 14 13 12 11 10 9 8 ? ? ? ? ????? r0 f 2 mc-16lx bus delayed interrupt cause issuance / cancellation decoder interrupt cause latch
mb90370/375 series 104 24. rom correction function when an address matches the value set in the address detection register, the instruction code to be loaded into the cpu is forced to be replaced with the int9 instruction code (01 h ) . when executing a set instruction, the cpu executes the int9 instruction. the rom correction function is implemented by processing using the int9 interrupt routine. the device contains two address detection registers, each provided with a compare enable bit. when the value set in the address detection register matches an address and the interrupt enable bit is 1, the instruction code to be loaded into the cpu is forced to be replaced with the int9 instruction code. (1) register configuration (continued) program address detection control / status register program address detection register 0 (upper byte) program address detection register 0 (middle byte) program address detection register 0 (lower byte) bit number address : 00009e h pacsr read/write initial value bit number address : 001ff2 h padrh0 read/write initial value bit number address : 001ff1 h padrm0 read/write initial value bit number address : 001ff0 h padrl0 read/write initial value ? ? ? ? ? ? r/w 0 r/w 0 r/w 0 r/w 0 76543210 ? ? ? ??? ad1e ad1d ad0e ad0d r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 r/w x
mb90370/375 series 105 (continued) (2) block diagram program address detection register 1 (upper byte) program address detection register 1 (middle byte) program address detection register 1 (lower byte) bit number address : 001ff5 h padrh1 read/write initial value bit number address : 001ff4 h padrm1 read/write initial value bit number address : 001ff3 h padrl1 read/write initial value r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x 76543210 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 r/w x f 2 mc-16lx bus address latch address detection register 0/1 ad0e/ad1e ad0d/ad1d pacsr comparator int9 command f 2 mc-16lx cpu
mb90370/375 series 106 25. rom mirroring function selection module the rom mirroring function selection module can select what the ff bank allocated the rom sees through the 00 bank according to register settings. (1) register configuration (2) block diagram rom mirror function selection register bit number address : 0006f h romm read/write initial value ? ? ? ? ? ? ? ? ? ? ? ? w 1 15 14 13 12 11 10 9 8 ? ? ? ? ????? m1 f 2 mc-16lx bus rom mirroring register address area ff bank 00 bank rom
mb90370/375 series 107 26. 512k bit flash memory the 512k bit flash memory is allocated in the ff h banks on the cpu memory map. like masked rom, flash memory is read-accessible and program-accessible to the cpu using the flash memory interface circuit. the flash memory can be programmed/erased by the instruction from the cpu via the flash memory interface circuit. the flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated cpu control, allowing program code and data to be improved efficiently. note that sector operations such as enable sector protect cannot be used. features of 512k bit flash memory : ? 64 kwords 8 bits / 32 kwords 16 bits (16 k + 8 k + 8 k + 32 k) sector configuration ? automatic program algorithm (same as the embedded algorithm* : mbm29f400ta) ? installation of the deletion temporary stop/delete restart function ? write/delete completion detected by the data polling or toggle bit ? write/delete completion detected by the cpu interrupt ? compatibility with the jedec standard-type command ? each sector deletion can be executed (sectors can be freely combined) . ? number of write/delete operations 10,000 times guaranteed * : embedded algorithm is a trademark of advanced micro devices, inc. (1) register configuration flash memory control status register bit number address : 0000ae h fmcs read/write initial value r/w 0 r/w 0 r 1 w 0 r/w 0 w 0 r/w 0 76543210 rdyint r/w 0 inte we rdy reserved lpm1 reserved lpm0
mb90370/375 series 108 (2) sector configuration of 512k bits flash memory the 512k bits flash memory has the sector configuration illustrated below. the addresses in the illustration are the upper and lower addresses of each sector. when accessed from the cpu, sa0 and sa1 to sa3 are allocated in the ff bank registers, respectively. * : writer addresses correspond to cpu addresses when data is programmed in flash memory by a parallel writer. writer addresses are used to program/erase data using a general-purpose writer. sa3 (16 kbytes) sa2 (8 kbytes) sa1 (8 kbytes) sa0 (32 kbytes) flash memory cpu address *writer address ffffff h 7ffff h ffc000 h ffbfff h ffa000 h ff9fff h ff8000 h ff7fffh ff0000 h 7c000 h 7bfff h 7a000 h 79fff h 78000 h 77fff h 70000 h
mb90370/375 series 109 n n n n electrical characteristics 1. absolute maximum ratings (v ss = av ss = cv ss = 0.0 v) (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 4.0 v cv cc v ss - 0.3 v ss + 4.0 v v cc 3 cv cc * 1 av cc v ss - 0.3 v ss + 4.0 v v cc 3 av cc * 1 a/d converter reference input voltage avr v ss - 0.3 v ss + 4.0 v av cc 3 avr, avr 3 av ss comparator reference input voltage cvrh1 cvrh2 cvrl v ss - 0.3 v ss + 4.0 v cv cc 3 cvrh1, cvrh1 3 cv ss cv cc 3 cvrh2, cvrh2 3 cv ss cv cc 3 cvrl, cvrl 3 cv ss lcd power supply voltage v1 to v3 v ss - 0.3 v ss + 4.0 v v1 to v3 must not exceed v cc not for mb90f377 input voltage v i1 v ss - 0.3 v ss + 4.0 v all pins except p40 to p45, p80 to p82, p90 to p95 * 2 v i2 v ss - 0.3 v ss + 6.0 v p40 to p45, p80 to p82, p90 to p95 output voltage v o v ss - 0.3 v ss + 4.0 v *2 maximum clamp current i clamp - 2.0 + 2.0 ma *4 total maximum clamp cur- rent s |i clamp | ? 20 ma *4 l level maximum output current i ol1 ? 10 ma all pins except pf0 to pf7* 3 i ol2 ? 20 ma pf0 to pf7* 3 l level average output current i olav1 ? 4ma all pins except pf0 to pf7 average output current = operating current operating efficiency i olav2 ? 12 ma pf0 to pf7 average output current = operating current operating efficiency l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma average output current = operating current operating efficiency h level maximum output current i oh ?- 10 ma *3 h level average output current i ohav ?- 3ma average output current = operating current operating efficiency h level total maximum output current s i oh ?- 100 ma h level total average output current s i ohav ?- 50 ma average output current = operating current operating efficiency
mb90370/375 series 110 (continued) (v ss = av ss = cv ss = 0.0 v) *1 : set av cc , cv cc and v cc at the same voltage. take care so that avr, cvrh1, cvrh2 and cvrl do not exceed v cc + 0.3 v when the power is turned on. *2 : v i and v o shall never exceed v cc + 0.3 v. v i should not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *3 : the maximum output current is a peak value for a corresponding pin. *4 : applicable to pins : p00 to p07, p10 to p17, p20 to p27, p30 to p37, p47, p50 to p57, p60 to p67, p70 to p77, pa0 to pa6, pc3 to pc7, pd0 to pd3, pd6, pd7 use within recommended operating conditions. use at dc voltage (current) . the + b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. care must be taken not to leave the + b input pin open. note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. sample recommended circuits : warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rting unit remarks min max power consumption p d ? 200 mw operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c input/output equivalent circuits vcc p-ch r n-ch +b input (0v to 16v) limiting resistance protective diode
mb90370/375 series 111 2. recommended operating conditions (v ss = av ss = cv ss = 0.0 v) *1 : set av cc , cv cc and v cc at the same voltage. *2 : take care so that avr, cvrh1, cvrh2 and cvrl do not exceed v cc + 0.3 v when power is turned on. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage * 1 v cc 3.0 3.6 v normal operation assurance range cv cc 3.3 3.6 v v cc 1.8 3.6 v retains the ram state in stop mode a/d converter reference input voltage * 2 avr 0 av cc v normal operation assurance range lcd power supply voltage v1 to v3 v ss v cc v v1 to v3 pins (the optimum value is dependent on the lcd element in use.) not for mb90f377 operating temperature t a - 40 + 85 c
mb90370/375 series 112 3. dc characteristics (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max h level input voltage v ih p10 to p17 p20 to p27 p30 to p37 p46, p47 p50 to p57 pa0 to pa6 pb0 to pb7 pc0 to pc7 pd0 to pd7 pf0 to pf7 ? 0.7 v cc ? v cc + 0.3 v cmos input pins v ihs p00 to p07 p60 to p67 p70 to p77 pe0 to pe7 rst 0.8 v cc ? v cc + 0.3 v cmos hysteresis input pins v ihs5 p40 to p45 0.8 v cc ? v ss + 5.5 v 5 v tolerant cmos hysteresis input pins v ih5 p82 0.7 v cc ? v ss + 5.5 v 5 v tolerant cmos input pin v ihsm p80, p81 p90 to p95 2.1 ? v ss + 5.5 v smbus input pins v ihm md0 to md2 v cc - 0.3 ? v cc + 0.3 v mode pins l level input voltage v il p10 to p17 p20 to p27 p30 to p37 p46, p47 p50 to p57 p82 pa0 to pa6 pb0 to pb7 pc0 to pc7 pd0 to pd7 pf0 to pf7 v ss - 0.3 ? 0.3 v cc v cmos input pins v ils p00 to p07 p40 to p45 p60 to p67 p70 to p77 pe0 to pe7 rst v ss - 0.3 ? 0.2 v cc v cmos hysteresis input pins
mb90370/375 series 113 (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max l level input voltage v ilsm p80, p81 p90 to p95 ? v ss - 0.3 ? 0.8 v smbus input pins v ilm md0 to md2 v ss - 0.3 ? v ss + 0.3 v mode pins open-drain output pin application voltage v d5 p40 to p45 p80 to p82 p90 to p95 v ss - 0.3 ? v ss + 5.5 v v d p46 v ss - 0.3 ? v cc + 0.3 v h level output voltage v oh1 all port pins except p40 to p46 p80 to p82 p90 to p95 pf0 to pf7 v cc = 3.0 v i oh1 = - 4.0 ma v cc - 0.5 ?? v v oh2 pf0 to pf7 v cc = 3.0 v i oh2 = - 8.0 ma v cc - 0.5 ?? v l level output voltage v ol1 all port pins except pf0 to pf7 i ol1 = 4.0 ma ?? 0.4 v v ol2 pf0 to pf7 i ol2 = 12.0 ma ?? 0.4 v input leakage current (high-z output leakage current) i il all input pins v cc = 3.3 v, v ss < v i < v cc - 5 ?+ 5 m a open-drain output leakage current i leak p40 to p46 p80 to p82 p90 to p95 ??? 5 m a power supply current* i cc v cc v cc = 3.3 v, internal operation at 16 mhz ? 37 45 ma mb90f372 / f377 ? 30 35 ma mb90372 i ccs v cc = 3.3 v, internal operation at 16 mhz, in sleep mode ? 15 20 ma i ccl v cc = 3.3 v, external 32 khz, internal operation at 8 khz, in sub-clock mode, t a = + 25 c ? 23 80 m a
mb90370/375 series 114 (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max power supply current* i ccls v cc v cc = 3.3 v, external 32 khz, internal operation at 8 khz, in sub-clock sleep mode, t a = + 25 c ? 10 50 m a i ccwat v cc = 3.3 v, external 32 khz, internal operation at 8 khz, in watch mode, t a = + 25 c ? 1.5 30 m a i cct v cc = 3.3 v, internal operation at 16 mhz, in timebase timer mode ? 1.3 2 ma i cch v cc = 3.3 v, in stop mode, t a = + 25 c ? 120 m a input capacitance c in all input pins except v cc , av cc , cv cc , v ss , av ss , cv ss ?? 515pf lcd divided resistance r lcd ? between v cc and v3 at v cc = 3.3 v 100 200 400 k w not for mb90f377 between v3 and v2 between v2 and v1 between v1 and v ss at v cc = 3.3 v 50 100 200 com0 to com3 output impedance r vcom com0 to com3 v1 to v3 = 3.3 v ?? 5k w not for mb90f377 seg0 to seg8 output impedance r vseg seg0 to seg8 ?? 5k w lcd leakage current l lcdl v1 to v3 com0 to com3 seg0 to seg8 ??? 1 m a not for mb90f377
mb90370/375 series 115 (continued) (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) * : the power supply current is measured with an external clock. parameter symbol pin name condition value unit remarks min typ max pull-up resistance r up p00 to p07 p10 to p17 p20 to p27 p30 to p37 rst ? 25 50 100 k w pull-down resistance r down md2 ? 25 50 100 k w mb90v370, mb90372 only
mb90370/375 series 116 4. ac characteristics (1) clock timings (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) * : when selecting the pll clock, the range of clock frequency is limited. use this product within range as mentioned in relationship between oscillating frequency and internal operating clock frequency of pll operation guarantee range. parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 3 ? 16 mhz crystal oscillator* f ch x0, x1 3 ? 32 mhz external clock* f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 31.25 ? 333 ns t lcyl x0a, x1a ? 30.5 ?m s input clock pulse width p wh p wl x0 5 ?? ns recommend duty ratio of 30 % to 70 % p whl p wll x0a ? 15.2 ?m s recommend duty ratio of 30 % to 70 % input clock rise/fall time t cr t cf x0 ?? 5ns external clock operation internal operating clock frequency f cp ? 1.5 ? 16 mhz main clock operation f lcp ?? 8.192 ? khz sub-clock operation internal operating clock cycle time t cp ? 62.5 ? 666 ns main clock operation t lcp ?? 122.1 ?m s sub-clock operation x0 t hcyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t lcyl t cf t cr 0.8 v cc 0.2 v cc p whl p wll x0, x1 clock timing x0a, x1a clock timing
mb90370/375 series 117 3.6 3.0 16 12 9 8 4 1.5 4 4 38 16 16 operation guarantee range of pll internal operating clock f cp (mhz) power supply voltage v cc (v) multiplied- by-4 multiplied- by-3 multiplied- by-2 oscillation clock f c (mhz) multiplied- by-1 not multiplied internal operating clock f cp (mhz) 8 normal operation guarantee range ? pll operation guarantee range relationship between internal operating clock frequency and power supply voltage relationship between oscillating frequency and internal operating clock frequency
mb90370/375 series 118 the ac ratings are measured for the following measurement reference voltages : 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc 2.1 v 0.8 v ? input signal waveform ? output signal waveform cmos input pin smbus input pin hysteresis input pin output pin
mb90370/375 series 119 (2) reset input timing (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) * : oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. in the crystal oscillator, the oscillation time is between several ms to tens of ms. in far/ceramic oscillator, the oscillation time is between hundreds of m s to several ms. in the external clock, the oscillation time is 0 ms. parameter symbol pin name condition value unit remarks min max reset input time t rstl rst ? 16 t cp ? ns normal operation oscillation time of oscillator* + 16 t cp ? ms in stop mode and sub-clock mode rst x0 16 t cp 0.2 vcc 0.2 vcc t rstl 90% of the oscillation amplitude internal operation clock oscillation time of oscillator oscillator stabilization time instruction execution internal reset ? in stop mode and sub-clock mode
mb90370/375 series 120 (3) power-on reset (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) * : v cc must be kept lower than 0.2 v before power-on. notes : the above values are used for causing a power-on reset. some registers in the device are initialized only upon a power-on reset. to initialize these registers, turn on the power supply using the above values. make sure that power supply rises within the selected oscillation stabilization time. if the power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol pin name condition value unit remarks min max power supply rise time t r v cc * ? ? 50 ms power supply cut-off time t off v cc *1 ? ms due to repeated operations t r t off v cc v cc v ss 0.2 v 1.8 v 2.2 v 0.2 v ram data hold 0.2 v sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommneded to raise the voltage smoothly to suppress fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 v or fewer per second, however, you can use the pll clock. it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower.
mb90370/375 series 121 (4) uart1 to uart3 (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) notes : these are ac ratings in the clk synchronous mode. c l is the load capacitance value connected to pins while testing. t cp is the internal operating clock cycle time. parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc uck1 to uck3 c l = 80 pf + 1 ttl for an output pin of internal shift clock mode 8 t cp ? ns uck ? uo delay time t slov uck1 to uck3 uo1 to uo3 - 80 + 80 ns valid ui ? uck - t ivsh uck1 to uck3 ui1 to ui3 100 ? ns uck - ? valid ui hold time t shix uck1 to uck3 ui1 to ui3 t cp ? ns serial clock h pulse width t shsl uck1 to uck3 c l = 80 pf + 1 ttl for an output pin of external shift clock mode 4 t cp ? ns serial clock l pulse width t slsh uck1 to uck3 4 t cp ? ns uck ? uo delay time t slov uck1 to uck3 uo1 to uo3 ? 150 ns valid ui ? uck - t ivsh uck1 to uck3 ui1 to ui3 60 ? ns uck - ? valid ui hold time t shix uck1 to uck3 ui1 to ui3 60 ? ns
mb90370/375 series 122 uck uo ui t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc uck uo ui t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc ? external shift clock mode ? internal shift clock mode
mb90370/375 series 123 (5) resources input timing (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) (6) trigger input timing (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min max timer input pulse width t tiwh t tiwl tin1 to tin4 ? 4 t cp ? ns parameter symbol pin name condition value unit remarks min max input pulse width t trgh t trgl adtg int0 to int5 ksi0 to ksi7 ? 5 t cp ? ns normal operation 1 ?m s stop mode 0.8 v cc tin1 to tin4 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl 0.8 v cc int0 to int5 ksi0 to ksi7 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl 0.7 v cc adtg 0.7 v cc 0.3 v cc 0.3 v cc t trgh t trgl
mb90370/375 series 124 (7) i 2 c / mi 2 c timing (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) *1 : at the stop condition or transferring of next byte. *2 : after setting register bit ibcrh : scc/mbcrh : scc at restart. *3 : t dosu is longer than the l width of scl. notes : t cp is the internal operating clock cycle time. m is the setting bit of shift clock oscillation defined in the iccr register (cs4 to cs3) and mccr register (cs4 to cs3) . please refer to the mb90370/375 series h/w manual for details. n is the setting bit of shift clock oscillation defined in the iccr register (cs2 to cs0) and mccr register (cs2 to cs0) . please refer to the mb90370/375 series h/w manual for details. sda and scl output value is specified on condition that the rise/fall time is 0 ns. parameter symbol pin name value unit remarks min max start condition output t sta scl sda t cp (m n/2 - 1) - 20 t cp (m n/2 - 1) + 20 ns master mode stop condition output t sto scl sda t cp (m n/2 + 3) - 20 t cp (m n/2 + 3) + 20 ns master mode start condition detect t sta scl sda t cp + 40 ? ns stop condition detect t sto scl sda t cp + 40 ? ns restart condition output t stasu scl sda t cp (m n/2 + 3) - 20 t cp (m n/2 + 3) + 20 ns master mode restart condition detect t stasu scl sda t cp + 40 ? ns scl output l width t low scl t cp m x n/2 - 20 t cp m n/2 + 20 ns master mode scl output h width t high scl t cp (m n/2 + 2) - 20 t cp (m n/2 + 2) + 20 ns master mode sda output delay t do sda t cp 3 - 20 t cp 3 + 20 ns sda output setup time after interrupt t dosu * 3 sda t cp m n/2 - 20 ? ns *1 t cp 4 - 20 ? ns *2 scl input l pulse t low scl t cp 3 + 40 ? ns scl input h pulse t high scl t cp + 40 ? ns sda output setup time t su sda 40 ? ns sda hold time t ho sda 0 ? ns
mb90370/375 series 125 sda scl sda scl t do t do t do t do t sto t ho t ho t low t low t high t sta t stasu t su t su t ho t dosu t dosu ack ack 9 9 8 7 6 1 ? data transmit (master / slave) ? data receive (master / slave)
mb90370/375 series 126 (8) ps/2 interface timing (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) note : t cp is the internal operating clock cycle time. parameter symbol pin name condition value unit remarks min typ max psck clock cycle time t pcyc psck0 to psck2 psda0 to psda2 ? 4 t cp ?? ns psck ? psda t plov psck0 to pscck2 psda0 to psda2 transmission mode 2 t cp ?? ns valid psda ? psck t pivsh psck0 to psck2 psda0 to psda2 reception mode 1 t cp ?? ns psck ? valid psda hold time t phix psck0 to psck2 psda0 to psda2 1 t cp ?? ns psck clock h pulse width t phsl psck0 to psck2 psda0 to psda2 ? 2 t cp ?? ns psck clock l pulse width t plsh psck0 to psck2 psda0 to psda2 2 t cp ?? ns psck0 psck1 psck2 psda0 psda1 psda2 psda0 psda1 psda2 0.8 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc t pcyc t plov t pivsh t phix ? transmission mode ? reception mode
mb90370/375 series 127 (9) lpc timing (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max lclk cycle time t cycle ?? 30 ?? ns lclk high time t high ?? 12 ?? ns lclk low time t low ?? 12 ?? ns t cycle t high t low 0.7 v cc 0.3 v cc lclk lclk ac timing
mb90370/375 series 128 0.4 v cc t val t on t off 0.4 v cc t s t h lclk output delay tri-state output lclk input lad, lframe , ga20 ac timing
mb90370/375 series 129 5. a/d converter electrical characteristics (2.7 v avr - av ss , v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) * : the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avr = 3.0 v) . parameter symbol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb non-linear error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an11 av ss - 1.5 lsb av ss + 0.5 lsb av ss + 5.5 lsb mv for mb90v370 av ss + 2.5 lsb for mb90f372/f377/372 full-scale transition voltage v fst an0 to an11 avr - 3.5 lsb avr - 1.5 lsb avr + 0.5 lsb mv conversion time ?? 3.1 ??m s actual value is specified as a sum of values specified in adcr0 : ct1, ct0 and adcr0 : st1, st0. be sure that the setting value is greater than the min value. sampling period ?? 2 ??m s actual value is specified in adcr0 : st1, st0 bits. be sure that the setting value is greater than the min value. analog port input current i ain an0 to an11 ? 0.1 10 m a analog input voltage v ain an0 to an11 av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v power supply current i a av cc ? 1.4 6.4 ma i ah ?? 5 m a* reference voltage supply current i r avr ? 94 300 m a i rh ?? 5 m a* offset between channels an0 to an11 ?? 4lsb
mb90370/375 series 130 6. a/d converter glossary (continued) resolution : analog changes that are identifiable with the a/d converter. linearity error : the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics. differential linearity error : the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value. total error : the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 0.5 lsb 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} actual conversion value (measured value) actual conversion value theoretical characteristics digital output analog input total error total error for digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (theoretical value) avr - avss 1024 [v] v ot (theoretical value) = avss + 0.5 lsb [v] v fst (theoretical value) = avr - 1.5 lsb [v] v nt : voltage at a transition of digital output from (n - 1) to n
mb90370/375 series 131 (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n - 1 n - 2 v ot (measured value) {1 lsb (n - 1) + v ot } actual conversion value v fst (measured value) v nt (measured value) actual conversion value theoretical characteristics actual conversion value actual conversion value theoretical characteristics digital output digital output analog input analog input v nt (measured value) v (n + 1) t (measured value) linearity error differential linearity error linearity error of digital output n v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] = differential linearity error of digital output n v (n + 1) t - v nt 1 lsb - 1 [lsb] = v fst - v ot 1022 [v] 1 lsb = v ot : voltage at transition of digital output from 000 h to 001 h v fst : voltage at transition of digital output from 3fe h to 3ff h
mb90370/375 series 132 7. notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions. output impedance values of the external circuit of 4 k w or lower are recommended. when capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. when the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient. ? error the smaller the | avr - av ss | is, the greater the error would become relatively. 8. d/a electrical characteristics (v cc = av cc = cv cc = 3.0 v to 3.6v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) * : with load capacitance is 20 pf. parameter symbol pin name condition value unit remarks min typ max resolution ?? ? ? 8 ? bit differential linearity error ?? ?? 0.9 lsb non-linearity error ?? ?? 1.5 lsb conversion time ?? ? 0.6 ?m s* analog output impedance ?? 2.0 2.9 3.8 k w power supply i dvr av cc ?? 460 m a current i dvrs av cc ? 0.1 ?m a d/a stops c comparator analog input r sampling and hold circuit ? equipment of analog input circuit model r : about 1.9 k w c : about 32.3 pf note : listed values must be considered as standards.
mb90370/375 series 133 9. comparator electrical characteristics (v cc = av cc = cv cc = 3.3 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) *: please use the reference voltage of cvrh2, cvrh1 and cvrl to 0.5v cc for mb90f377. 10. serial irq electrical characteristics (v cc = av cc = cv cc = 3.0 v to 3.6 v, v ss = av ss = cv ss = 0.0 v, t a = - 40 c to + 85 c) 11. flash memory program/erase characteristics parameter symbol pin name condition value unit remarks min typ max reference voltage ? cvrh2 ? 1.1 ? 2.9 v * cvrh1 cvrl ? 2.9 v cvrl 1.1 ? cvrh1 v reference voltage supply current i cr cvrh2 cvrh1 cvrl ??? 1 m a comparator supply current i cv cv cc ? ?? 50 m aactive ?? 10 m a inactive analog input voltage v ih dcin dcin2 vol1 to vol3 vsi1 to vsi3 ? cv ss ? cv cc v parameter symbol pin name condition value unit remarks min typ max h level input voltage v ih ?? 0.7v cc ? v cc v l level input voltage v il ?? v ss ? 0.3v cc v h level output voltage v oh ?? v cc - 0.5 ?? v l level output voltage v ol ???? 0.4 v parameter condition value unit remarks min typ max sector erase time t a = + 25 c v cc = 3.0 v ? 115s excludes 00 h programming prior to erasure chip erase time ? 4 ? s excludes 00 h programming prior to erasure word (16 bit width) programing time ? 16 3,600 m s except for the over head time of the system program/erase cycle ? 10,000 ?? cycle
mb90370/375 series 134 n n n n example characteristics ?mb90f372 (continued) 50.0 40.0 30.0 20.0 10.0 0.0 2.0 3.0 4.5 4.0 2.5 i cc (ma) v cc (v) ta 25 c 3.5 f ch = 16.0 mhz f ch = 12.0 mhz f ch = 4.0 mhz f ch = 2.0 mhz f ch = 10.0 mhz f ch = 8.0 mhz 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 2.0 3.0 4.5 4.0 2.5 i ccs (ma) v cc (v) ta 25 c 3.5 f ch = 16.0 mhz f ch = 10.0 mhz f ch = 8.0 mhz f ch = 4.0 mhz f ch = 2.0 mhz f ch = 12.0 mhz 30.0 25.0 20.0 15.0 10.0 5.0 0.0 2.0 3.0 4.5 4.0 2.5 i ccl ( a) v cc (v) ta 25 c 3.5 f cl = 32.0 khz v cc vs. i cc v cc vs. i ccs v cc vs. i ccl
mb90370/375 series 135 (continued) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 -4 -10 -8 -2 v cc - v oh2 (v) i oh2 (ma) ta 25 c -6 vcc = 3.0 v vcc = 3.5 v vcc = 2.5 v 0.8 0.6 0.4 0.2 0.0 04 10 8 2 v ol1 (v) i ol1 (ma) ta 25 c 6 vcc = 3.0 v vcc = 3.5 v vcc = 2.5 v 0.3 0.2 0.1 0.0 04 10 8 2 v ol2 (v) i ol2 (ma) ta 25 c 6 vcc = 3.0 v vcc = 3.5 v vcc = 2.5 v i oh2 vs. v cc - v oh2 i ol1 vs. v ol1 i ol2 vs. v ol2 2.0 1.5 1.0 0.5 0.0 0-4-8 -2 v cc - v oh1 (v) i oh1 (ma) ta 25 c -6 -10 vcc = 2.5 v vcc = 3.0 v vcc = 3.5 v i oh1 vs. v cc - v oh1
mb90370/375 series 136 ? mb90372t (continued) 40.0 30.0 20.0 10.0 0.0 1.5 3.0 4.5 4.0 2.5 i cc (ma) v cc (v) ta 25 c 3.5 f ch = 16.0 mhz f ch = 10.0 mhz f ch = 8.0 mhz f ch = 4.0 mhz f ch = 12.0 mhz f ch = 2.0 mhz 2.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 1.5 3.0 4.5 4.0 2.5 i ccs (ma) v cc (v) ta 25 c 3.5 f ch = 16.0 mhz f ch = 10.0 mhz f ch = 8.0 mhz f ch = 4.0 mhz f ch = 12.0 mhz f ch = 2.0 mhz 2.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 1.5 3.0 4.5 4.0 2.5 i ccl ( m a) v cc (v) ta = + 25 c 3.5 2.0 f cl = 32.0 khz v cc vs. i cc v cc vs. i ccs v cc vs. i ccl
mb90370/375 series 137 (continued) 0.4 0.3 0.2 0.1 0.0 0-4-8 -2 v cc - v oh2 (v) i oh2 (ma) ta 25 c -6 -10 vcc = 2.5 v vcc = 3.0 v vcc = 3.5 v 0.8 0.6 0.4 0.2 0.0 048 2 v ol1 (v) i ol1 (ma) ta 25 c 6 10 vcc = 2.5 v vcc = 3.0 v vcc = 3.5 v 0.25 0.20 0.15 0.10 0.05 0.0 048 2 v ol2 (v) i ol2 (ma) ta 25 c 6 10 vcc = 2.5 v vcc = 3.0 v vcc = 3.5 v i oh2 vs. v cc - v oh2 i ol1 vs. v ol1 i ol2 vs. v ol2 1.0 0.8 0.6 0.4 0.2 0.0 0-4-8 -2 v cc - v oh1 (v) i oh1 (ma) ta 25 c -6 -10 vcc = 2.5 v vcc = 3.0 v vcc = 3.5 v i oh1 vs. v cc - v oh1
mb90370/375 series 138 n n n n ordering information part number package remarks mb90f372pff-g MB90F377PFF-G mb90372pff-g-xxx 144-pin plastic lqfp (fpt-144p-m12) xxx is the rom release number.
mb90370/375 series 139 n n n n package dimension 144-pin plastic lqfp (fpt-144p-m12) note 1) * : these dimensions include resin protrusion. resin protrusion is +0.25(.010)max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches). note: the values in parentheses are reference values. c 2003 fujitsu limited f144024s-c-3-3 .059 C .004 +.008 C 0.10 +0.20 1.50 details of "a" part 0~8 ? (mounting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0.08(.003) 0.145 C 0.03 +.002 C .001 .006 +0.05 "a" .007.001 0.180.035 m 0.07(.003) 36 37 1 lead no. 0.40(.016) index 144 109 108 18.000.20(.709.008)sq sq 16.00 73 72 * .630 C .004 +.016 C 0.10 +0.40
mb90370/375 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0402 ? fujitsu limited printed in japan

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